Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.
DOI: 10.1109/cicc.2003.1249464
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A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES

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Cited by 3 publications
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“…This process is called bit synchronization. The most common technique to establish bit synchronization is to use a phase locked loop (PLL) [10][11][12][13][14][15]. This can either be a clock-and-data recovery (CDR, see Fig.…”
Section: Bit Synchronizationmentioning
confidence: 99%
“…This process is called bit synchronization. The most common technique to establish bit synchronization is to use a phase locked loop (PLL) [10][11][12][13][14][15]. This can either be a clock-and-data recovery (CDR, see Fig.…”
Section: Bit Synchronizationmentioning
confidence: 99%