A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

Law, Chong-Fatt; Rofail, S.S.; Yeo, Kiat Seng

doi:10.1109/4.792613

Cited by 30 publications

(10 citation statements)

References 12 publications

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“…Pass transistor logic (PTL) and especially complementary pass transistor logic (CPL) have become popular since they oOE er the possibility to implement high speed and low power circuits in certain applications. The popularity of these logic styles is indicated by the large number of circuits developed recently with increased performance in terms of speed and power e ciency (Yano et al 1990, Suzuki et al 1993, Ko et al 1995, Abu-Khater et al 1996, Law et al 1999). In addition, during the past few years research has also focused on the development of synthesis methodologies that target pass transistor implementations starting from technology-independen t descriptions such as hardware description languages (HDLs) (Yano et al 1996, Ferrandi et al 1998, Jaekel et al 1998, Zhuang et al 1999.…”

Section: Introductionmentioning

confidence: 98%

Modelling the operation of pass transistor and CPL gates

Chatzigeorgiou¹,

Nikolaidis²

2001

International Journal of Electronics

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Pass transistor logic and complementary pass-transistor logic (CPL) are becoming increasingly important in the design of a speci® c class of digital integrated circuits owing to their speed and power e ciency as compared with conventional CMOS logic. In this paper, a simple and very accurate technique for the timing analysis of gates that involve pass transistor logic is presented. This investigation oOE ers for the ® rst time the possibility of simulating pass transistor and CPL gates by partitioning the behaviour of complex structures into well de® ned subcircuits whose interaction is studied separately. Using the proposed analysis, which is validated by results for two submicron technologies, most pass-transistor logic styles can be modelled e ciently. Consequently, a signi® cant speed advantage can be gained compared with simulation tools that employ numerical methods such as SPICE.

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Section: Introductionmentioning

confidence: 98%

Modelling the operation of pass transistor and CPL gates

Chatzigeorgiou¹,

Nikolaidis²

2001

International Journal of Electronics

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“…There are many proposed logics (or) low power dissipation and high speed and each logic style has its own advantages in terms of speed and power [6] [7]. Fast multipliers are a key topic in the VLSI design of high speed processors [8].…”

Section: Introductionmentioning

confidence: 99%

A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics

Vaidya¹,

Dandekar²

2011

Proceedings of the 2011 International Conference on Communication, Computing &Amp; Security - ICCCS '11

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In this paper, low power and high speed 8×8 Bit Vedic Multiplier is presented. A Novel technique for digit multiplication is produced that is quite different from the conventional method of multiplication like Add and Shift [1]. This paper presents a systematic design methodology for fast and delay efficient Vedic Multiplier based on Vedic Mathematics [2]. The multiplier architecture based on the Vertical and Crosswise algorithm of Ancient Indian Vedic Mathematics. In this paper, general technique for N×N multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8×8 Bit Vedic Multiplier. In this paper, less delay and high speed 8×8 Bit Vedic Multiplier is presented. The multiplier cell of the adder is designed by using Pass Transistor (n-transistor), ptransistor used as cross coupled devices. The 8×8 Bit Vedic Multiplier circuit has been simulated using Microwind 3.1 VLSI Layout CAD tools. Simulated results for proposed 8×8 bit Vedic Multiplier circuit shows a great reduction in delay for 0.18 μm.

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“…The three important considerations for VLSI design are power, area and delay. There are many proposed logics (or) low power dissipation and high speed and each logic style has its own advantages in terms of speed and power [6][7].…”

Section: Introductionmentioning

confidence: 99%