A low power 6-bit current-steering DAC in 0.18-&amp;#x03BC;m CMOS process

Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

doi:10.1109/isacv.2015.7106175

Cited by 7 publications

(1 citation statement)

References 8 publications

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“…The different kinds of ADCs architectures have been studied by several researchers [ 18 , 20 – 33 ]. The proposed ADCs architecture determines how well it can meet the below-mentioned targets.…”

Section: Introductionmentioning

confidence: 99%

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Chakir

Akhamal

Qjidaa

2017

The Scientific World Journal

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The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

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Section: Introductionmentioning

confidence: 99%

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Chakir

Akhamal

Qjidaa

2017

The Scientific World Journal

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Design and analysis of high performance 9 bit SAR ADC with SFDR 76.59

Adupa,

Mannepalli,

Ijjada

2022

INTERNATIONAL CONFERENCE ON RESEARCH IN SCIENCES, ENGINEERING &Amp; TECHNOLOGY

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A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

2022

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This paper introduces a current reference based on ∆V GS generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6 V with a line sensitivity equal to 1.2 %/V in the range [0.8-1.8] V and a temperature coefficient equal to 6.3 ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.INDEX TERMS Current reference, low voltage, low power, area-efficient, Internet of Things, sensor nodes, implanted biomedical devices NOMENCLATURE

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A low power 6-bit current-steering DAC in 0.18-μm CMOS process

Cited by 7 publications

References 8 publications

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Design and analysis of high performance 9 bit SAR ADC with SFDR 76.59

A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

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