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In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits,operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential nonlinearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is , .

With their many advantages, including low power dissipation in power switches, low harmonic content, and reduced electromagnetic interference (EMI) from the inverter, multilevel converter (MLI) topologies are becoming more and more in demand in high and medium power applications. This paper introduces a novel multi-level symmetric inverter topology with adopted control. The objectives of this article are to architecturally define the positions of the various switches, to choose the right switches and to propose an inverter control strategy that will eliminate harmonics while producing the ideal output voltage/current. By using fewer switching elements, fewer voltage sources, and switches with a total harmonic content (THD) which reduces losses and a drop in minimum voltage (Vstrssj), the proposed topology is more efficient than conventional inverters with the same number of levels. The new topology will be demonstrated using a seven-level single-phase inverter. For various modulation indices, MATLAB-SIMULINK is used to study and validate the topology.

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