1 GS/s, low power flash analog to digital converter in 90nm CMOS technology

Chakir, Mostafa; Qjidaa, Hassan

doi:10.1109/icmcs.2012.6320209

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…The proposed current-steering DAC is based on two blocks which are the current mirror circuit concept and switches, where the width of MSBs current source transistors is kept same as the width of LSBs [4,5,16,17]. The Overall Schematic of proposed CS-DAC is as shown in Fig.…”

Section: Proposed Architecture Of Cs-dacmentioning

confidence: 99%

A low power 6-bit current-steering DAC in 0.18-μm CMOS process

Chakir

Akhamal

Qjidaa

2015

2015 Intelligent Systems and Computer Vision (ISCV)

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In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits,operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential nonlinearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is , .

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Section: Proposed Architecture Of Cs-dacmentioning

confidence: 99%

A low power 6-bit current-steering DAC in 0.18-μm CMOS process

Chakir

Akhamal

Qjidaa

2015

2015 Intelligent Systems and Computer Vision (ISCV)

Self Cite

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“…Ultra wide band systems [4], magnetic and optical data storage devices [5], high speed instrumentation, wideband radar and optical communications [8], [12], 3G telecommunication systems, wireless wide area networks, broadband wireless communication network, radio astronomy, optical communication systems [6]. ADCs with high speed and resolution in the range of 6-8 bits are used in digital telecommunications, cryptography, high performance image sensing and processing, digital signal oscilloscopes and gigabit Ethernet.…”

Section: Introductionmentioning

confidence: 99%

“…New methods developed to reduce the power consumption of flash ADCs are [5]. -Extension in the input range.…”

Section: Introductionmentioning

confidence: 99%

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Sunaniya¹,

Khare²

2013

IJCA

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The Analog to Digital converters (ADC) play a very important role in today's world of electronic systems. The requirement of present applications demands high speed, low power dissipation, minimum area, low noise and application specific resolution. Out of the various types of ADCs available the flash ADC is most popular for its highest conversion rate and its wide applications. On the down side the flash ADC dissipates high power due to the presence of resistance ladder. The power dissipation further increases with increase in resolution. In this research two different approaches are presented which eliminates the resistor ladder completely and hence reduce the power demand drastically. The first approach is Switched Inverter Scheme (SIS) ADC; it is realized for 3 bits using 7 comparator circuits of varying size in CMOS 45nm technology with Predictive Technology Model (PTM). The test result obtained indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 µwatts; Power delay product (PDP) is 415.9 fWs, and the area overhead is 1.89µm 2 . The second approach is Sleep transistor SIS ADC. This approach shows 71% improvement in power dissipation. Whereas PDP is found to be 107.3 fWs and area overhead is 1.94 µm2 for Sleep transistor SIS ADC.

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“…High speed data converters are the key building blocks in many applications including high data rate serial links [2], [11]. Ultra wide band systems [4], magnetic and optical data storage devices [5], high speed instrumentation, wideband radar and optical communications [8], 3G telecommunication systems, wireless wide area networks, broadband wireless communication network, radio astronomy, optical communication systems [6]. ADCs with high speed and resolution in the range of 6-8 bits are used in digital telecommunications, cryptography, high performance image sensing and processing, digital signal oscilloscopes, gigabit Ethernet.…”

Section: Introductionmentioning

confidence: 99%

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

Sunaniya¹,

Khare

2013

VLSICS

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This work presents three different approaches which eliminates the resistor ladder completely and hencereduce the power demand drastically of a Analog to Digital Converter. The first approach is SwitchedInverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches areclocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in powerdissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SISADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC

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1 GS/s, low power flash analog to digital converter in 90nm CMOS technology

Cited by 4 publications

References 7 publications

A low power 6-bit current-steering DAC in 0.18-μm CMOS process

A low power 6-bit current-steering DAC in 0.18-μm CMOS process

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

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1 GS/s, low power flash analog to digital converter in 90nm CMOS technology

Cited by 4 publications

References 7 publications

A low power 6-bit current-steering DAC in 0.18-&#x03BC;m CMOS process

A low power 6-bit current-steering DAC in 0.18-&#x03BC;m CMOS process

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

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A low power 6-bit current-steering DAC in 0.18-μm CMOS process

A low power 6-bit current-steering DAC in 0.18-μm CMOS process