A Low-Power 65/14nm Stacked CMOS Image Sensor

Kwon, Minho; Lim, Sanghyeok; Lee, Hyeokjong; Ha, Il-Seon; Kim, Moo-Young; Seo, Il-Jin; Lee, Suho; Choi, Yongsuk; Kim, Kyunghoon; Lee, Hansoo; Kim, Won-Woong; Park, Seonghye; Koh, K.; Lee, Jesuk; Park, Yongin

doi:10.1109/iscas45731.2020.9180435

Cited by 12 publications

(14 citation statements)

References 8 publications

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“…The estimated hybrid bond density is about 5000 bonds/mm 2 . [32]. Its 108 MP BSI-CIS has been implemented in smartphones in 2019 using 65 nm technology for pixel array chip and 28 nm technology for logic chip [32].…”

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

“…[32]. Its 108 MP BSI-CIS has been implemented in smartphones in 2019 using 65 nm technology for pixel array chip and 28 nm technology for logic chip [32]. Samsung has moved toward 0.7 lm pixel on 65 nm technology with logic and signal processor on 14 nm FinFET technology recently.…”

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

“…Dualphotodiode pixels have each photodiode in size of 0.7 lm Â 1.4 lm leading to pixel size of 1.4 lm Â 1.4 lm as shown in Fig. 7 [32]. The disparity between left and right photodiode signals is used for phase shift detection autofocus data and the sum of them is used for the output image data [32].…”

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

“…7 [32]. The disparity between left and right photodiode signals is used for phase shift detection autofocus data and the sum of them is used for the output image data [32]. The increased complexity of logic and image processing is enabled through the use of 14 nm technology, allowing the same chip size with more functionality.…”

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

“…6 Schematics of Stacked BSI pixel chip to circuit chip bonded at dielectric surfaces with peripheral via-last TSVs Both applications are using stacked chip architecture with direct bonding followed by peripheral via-last TSV chip-to-chip interconnect. The scaling of the bottom logic chip can absorb more complicated ML/AI algorithms and wireless communication features [32].…”

Section: Dual Photodiodesmentioning

confidence: 99%

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Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS Image Sensors (CIS) for different functions such as visible light detection, Single Photon Avalanche Photodiode (SPAD) for low light detection, rolling shutter and global shutter, and depth sensing and Light Detection And Ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultra-high-density interconnect manufacturability is also highlighted.

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Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

Section: The Stacked Rgb Backside Illuminated-cmos Imagementioning

confidence: 99%

Section: Dual Photodiodesmentioning

confidence: 99%

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Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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In-sensor optoelectronic computing using electrostatically doped silicon

et al. 2022

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Complementary metal-oxide-semiconductor (CMOS) image sensors are a visual outpost of many machines that interact with the world. While they presently separate image capture in front-end silicon photodiode arrays from image processing in digital back-ends, efforts to process images within the photodiode array itself are rapidly emerging, in hopes of minimizing the data transfer between sensing and computing, and the associated overhead in energy and bandwidth. Electrical modulation, or programming, of photocurrents is requisite for such in-sensor computing, which was indeed demonstrated with electrostatically doped, but non-silicon, photodiodes. CMOS image sensors are currently incapable of in-sensor computing, as their chemically doped photodiodes cannot produce electrically tunable photocurrents. Here we report in-sensor computing with an array of electrostatically doped silicon p-i-n photodiodes, which is amenable to seamless integration with the rest of the CMOS image sensor electronics. This silicon-based approach could more rapidly bring in-sensor computing to the real world due to its compatibility with the mainstream CMOS electronics industry. Our wafer-scale production of thousands of silicon photodiodes using standard fabrication emphasizes this compatibility. We then demonstrate in-sensor processing of optical images using a variety of convolutional lters electrically programmed into a 3 × 3 network of these photodiodes. Main TextComplementary metal oxide semiconductor (CMOS) image sensors have become an indispensable part of our data-driven world, where visual information prevails 1,2 . The front-end silicon photodiode array in a CMOS image sensor converts light into electrical currents. These electrical data undergo analog-to-digital conversion and are then shuttled to a digital back-end for image processing. While this standard sequence of front-end image capture and back-end processing restricts the role of the photodiode array to sensing, emerging machine vision applications would bene t from data processing within the photodiode array itself 3,4 . For example, in object tracking for self-driving vehicles, drones, or robots, where only the edges of objects are relevant [5][6][7][8] , edge extraction in the front-end photodiode array would be much more economical in energy expenditure, processing latency, required bandwidth, and memory usage, as compared to transferring the whole image data containing super uous information to the back-end digital processor-only to extract the edges 9 . Such in-sensor computing would require an electrical modulation, or programming, of photocurrents. In fact, in-sensor computing has been recently demonstrated with electrostatically doped photodiodes whose photocurrents can be modulated with gate biasing 10,11 . These pioneering works have realized electrostatically doped photodiodes by gating two-dimensional (2D) transition metal dichalcogenide (TMD) layers or their van der Waals (vdW) stacks [12][13][14] . In contrast, such in-sensor computing is not possible with ...

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CMOS Image Sensors

Stefanov

2022

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List of frequently used abbreviations xvTable of common symbols and units xvi 1-58 Chapter summary 1-60 References 1-61 2 CMOS pixel architectures 2-1 2.1 History and technology 2-1 2.2 Photodiode APS 2-2 2.2.1 Structure 2-2 2.2.2 Operation 2-5 2.2.3 Performance 2-9 2.3 Pinned photodiode (4T) 2-11 2.3.1 Structure 2-11 2.3.2 Operation 2-15 2.3.3 Charge storage and full well capacity 2-17 2.3.4 Charge transfer 2-22 2.3.5 Image lag 2-27 2.3.6 Transistor sharing 2-33 2.4 Other PPD-based pixels 2-33 2.4.1 Global reset (5T) 2-33 2.4.2 In-pixel signal storage 2-35 2.4.3 High dynamic range 2-37 2.5 Hybrid and 3D image sensors 2-41 Chapter summary 2-43 References 2-44 3 Advanced image sensor topics 3-1

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A Low-Power 65/14nm Stacked CMOS Image Sensor

Cited by 12 publications

References 8 publications

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

In-sensor optoelectronic computing using electrostatically doped silicon

CMOS Image Sensors

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