A Low-Power Capacitive Charge Pump Based Pipelined ADC

Abstract

Abstract-A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

“…However, these techniques cannot be used for high-speed high-resolution ADCs due to limitations such as memory effects and an additional delay because of extra clock phases. Alternative techniques such as comparator-based and charge-pump based pipelined ADC architectures have been introduced together with calibrations to reduce the power consumption [53,54]. However, they are not appropriate for high resolution at high speeds.…”

A statistics-based digital background calibration technique for pipelined ADCs

“…So, the digital output, D out , encompasses the input voltage, V in , and only the ideal backend ADC quantization error, ε qbe . If the coefficients of g a were known, the coefficients of g d would be determined by using (9)- (11). In reality, the coefficient values of g a are totally sensitive to voltage drift and temperature variation.…”

“…Since the ADC offset is not an hazardous issue in communication systems, in simulations, the residue amplifier offset is neglected as in [1][2][3][4][5][9][10][11][12].…”

“…Because of low-power digital signal processing availability in modern CMOS technologies, digital compensation of analog circuit imperfections is becoming popular [9]. In order to correct conversion errors, different digital calibration techniques for pipelined ADCs have been proposed, such as [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17].…”

A Novel Method of Discrete-Time Signal Amplification Using NEMS Devices

“…Some of the reported works in which D-T amplification was performed without using op-amp are reported in [12]- [15]. In [12] comparator is used while [13] uses dynamic source follower, [14] employs charge pump technique and [15] utilizes MOS varactor. In this work we propose to utilize NEMS devices for performing D-T signal amplification.…”