A statistics-based digital background calibration technique for pipelined ADCs

Mafi, Hamidreza; Mohammadi, Reza Karami; Shamsi, Hossein

doi:10.1016/j.vlsi.2015.07.014

Cited by 9 publications

(1 citation statement)

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“…Using Verilog and digital design tools for synthesis fabricated on 130nm CMOS process, results were obtained in terms of SFDR and SNDR at 0.7V supply [12]. Another publication introduced and verified another technique of LMS algorithm (least mean squares) for background calibration for pipelined ADCs to correct conversion errors and DRDE (digitized residue distance estimation) algorithm [13]. The authors M.A.…”

Section: Figmentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Section: Figmentioning

confidence: 99%