A low-power comparator with programmable hysteresis level for blood pressure peak detection

Qian, Xinbo; Teo, T. Hui

doi:10.1109/tencon.2009.5396125

Cited by 31 publications

(13 citation statements)

References 8 publications

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“…Consequently, D out is in logic state 0. V h + and V h − are controlled via the width ratio a of transistor M 4– M 3 and the width ratio b of transistor M 5– M 6, respectively [14].…”

Section: Circuit Implementationmentioning

confidence: 99%

Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

Chen

Lin

et al. 2020

IET Circuits, Devices & Systems

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A reference-less ultra-low-power wake-up receiver (WuRx) is proposed for the highly integrated Internet of things applications. The WuRx utilises a direct radio-frequency envelope detection technique with input synchronised switching to suppress 1/f noise and enhance the sensitivity. Moreover, injection-locked clock and data recovery circuitry is used to perform on-chip clock generation. A prototype 2.4 GHz WuRx is designed and implemented with 90 nm complementary metal-oxidesemiconductor technology. The chip area is 1.0 × 0.95 mm 2. The measurement results show that the WuRx consumes 25 μW and achieves a sensitivity of −51.5 dBm for 200 kbps data rate.

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“…Consequently, D out is in logic state 0. V h + and V h − are controlled via the width ratio a of transistor M 4– M 3 and the width ratio b of transistor M 5– M 6, respectively [14].…”

Section: Circuit Implementationmentioning

confidence: 99%

Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

Chen

Lin

et al. 2020

IET Circuits, Devices & Systems

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“…To complete the REWARD algorithm, we paired the Rel-En method with a real-time peak detection procedure that is both adaptable and computationally simple. Our algorithm is based on the hysteresis comparator [17], and several optimizations are applied to improve its detection accuracy. The R-peaks are detected using a window of 1.75 s. Consequently, the initial delay of this algorithm is (0.95/2+1.75)s. For each R-peak detection window, the algorithm first checks if the dominant peak is positive or negative.…”

Section: B Reward Peak Detectionmentioning

confidence: 99%

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm

Orlandic

Giovanni

Arza

et al. 2019

2019 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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Wearable devices are an unobtrusive, costeffective means of continuous ambulatory monitoring of chronic cardiovascular diseases. However, on these resource-constrained systems, electrocardiogram (ECG) processing algorithms must consume minimal power and memory, yet robustly provide accurate physiological information. This work presents REWARD , the Relative-Energy-based WeArable R-Peak Detection algorithm, which is a novel ECG R-peak detection mechanism based on a nonlinear filtering method called Relative-Energy (Rel-En). REWARD is designed and optimized for real-time execution on wearable systems. Then, this novel algorithm is compared against three state-of-the-art real-time R-peak detection algorithms in terms of accuracy, memory footprint, and energy consumption. The Physionet QT and NST Databases were employed to evaluate the algorithms' accuracy and robustness to noise, respectively. Then, a 32-bit ARM Cortex-M3-based microcontroller was used to measure the energy usage, computational burden, and memory footprint of the four algorithms. REWARD consumed at least 63% less energy and 32% less RAM than the other algorithms while obtaining comparable accuracy results. Therefore, REWARD would be a suitable choice of R-peak detection mechanism for wearable devices that perform more complex ECG analysis, whose algorithms require additional energy and memory resources.

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“…The second pre-amplifier with the hysteresis function is shown in Fig. 4 [3]. This hysteresis circuit provides hysteresis voltages in a continuous comparator to overcome unexpected noise.…”

Section: High Speed Comparator In Normal Modementioning

confidence: 99%

Design of High-Speed Comparators for High-Speed Automatic Test Equipment

Yoon

Lim²

2015

IEIE Transactions on Smart Processing and Computing

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This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with 0.18μm Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is 0.514mm 2 .

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A low-power comparator with programmable hysteresis level for blood pressure peak detection

Cited by 31 publications

References 8 publications

Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm

Design of High-Speed Comparators for High-Speed Automatic Test Equipment

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