2019
DOI: 10.1109/tcsi.2018.2880363
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A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application

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Cited by 45 publications
(36 citation statements)
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“…A HW accelerator close to our work was recently published in [14]. The authors implement a HW accelerator in 65nm ASIC to train the last fully connected layers in the MDNET based object tracker similar to our work.…”
Section: Relu and Dropout Storagementioning
confidence: 95%
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“…A HW accelerator close to our work was recently published in [14]. The authors implement a HW accelerator in 65nm ASIC to train the last fully connected layers in the MDNET based object tracker similar to our work.…”
Section: Relu and Dropout Storagementioning
confidence: 95%
“…Our HW accelerator can be adopted to train other Multi-Layer Perception (MLP) neural networks that are employed in real-time applications on embedded devices. Some prior works [14], [23], [24] exist in literature to accelerate the training of the MLP or fully-connected neural networks. Approximate computing is adopted in [23] via inexact multipliers and bit-precision reduction to reduce the power consumption.…”
Section: Relu and Dropout Storagementioning
confidence: 99%
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“…Han et al design a dedicated processor for DNN-based real-time object tracking [70]. is processor achieves low power consumption through a DNN-specific processor architecture and a specialized algorithm.…”
Section: Hardware Revolutionmentioning
confidence: 99%
“…The large number of multi-bit elementary arithmetic operations performed by the vector-matrix multiplier (VMM) and the heavy data exchange between the memory and logic elements represent the main limiting factors of both EE and throughput in conventional digital CPU architectures [1], [2], [3], [4]. The recurring nature of these arithmetic operations can be exploited by taking advantage of the parallel computing capability of GPUs [5] and of embedded ASIC accelerators [6], [7]. Parallelism in computation and in memory access can be better exploited through in-memory computing architectures, consisting of a large number of modularized processing elements distributed in space and operating in parallel, where each processing element contains both the logic and the memory to perform the assigned partial processing task.…”
Section: Introductionmentioning
confidence: 99%