A low-power design methodology for high-resolution pipelined analog-to-digital converters

Lotfi, R.; Taherzadeh-Sani, M.; Azizi, M.Y.; Shoaei, O.

doi:10.1109/lpe.2003.1231890

Cited by 8 publications

(8 citation statements)

References 6 publications

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“…Equation (1) relates the power of the OTA to the sampling rate and I t can be optimized for minimum power dissipation [10]. In typical power scalable and reconfigurable ADCs, the bias currents of the OTAs are scaled with the sampling rate in order to maintain a constant SNDR.…”

Section: B Design Considerations In Conventional Adcsmentioning

confidence: 99%

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

Chandrashekar

Corsi

Fattaruso

et al. 2010

IEEE Trans. Circuits Syst. II

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A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μm CMOS process and occupies a die area of 1.9 mm 2 .

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Section: B Design Considerations In Conventional Adcsmentioning

confidence: 99%

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

Chandrashekar

Corsi

Fattaruso

et al. 2010

IEEE Trans. Circuits Syst. II

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“…2 is as follows [6] . It is worth mentioning that in the above formulation, we assume g m2 = g m3 and C a = C s .…”

Section: A Operational Amplifiermentioning

confidence: 99%

“…Reduction of the power dissipation looks even more challenging in low-voltage analog integrated circuits, as there will be less room for the signal and to keep the same signal-to-noise ratio, the power is to be increased [6]. Therefore, low-power design approaches for low-voltage fast-settling operational amplifiers in switched-capacitor applications can be very attractive.…”

Section: Introductionmentioning

confidence: 99%

“…We use a novel cascode compensation scheme called hybrid cascode compensation that has been introduced in [4] and reconsidered in [5,6]. In this method, two distinct capacitors are used between two low-impedance nodes of the first stage and the output node.…”

Section: Introductionmentioning

confidence: 99%

“…As shown in Fig. 2 two separate capacitors, C a and C s , have been used for compensation of the opamp where C a is used in a signal path and C s in a non-signal path [5,6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation

Zangeneh

Aghababa

Forouzandeh

2009

2009 European Conference on Circuit Theory and Design

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This paper presents a well-established low power sample & hold circuitry, implemented in 180-nm CMOS technology. This circuit uses a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifiers (OTAs). The circuit achieves minimum SNR of 74dB in all corner cases. Also average current dissipation of the whole circuit is measured to be 7.1mA in Typical-Typical corner case. SNR and total current dissipation of the circuit is calculated and listed in different corner cases. Although the sample and hold circuit meets the requirements of SNR specifications, this success does not seem to be outstanding. However, small amount of current dissipation which comes from the low-power OTA configuration is a great success.

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A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

Nanbakhsh

Maghami

Sheikhaei

et al. 2011

2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)

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A low-power design methodology for high-resolution pipelined analog-to-digital converters

Cited by 8 publications

References 6 publications

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

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