A low-power dynamic comparator for low-offset applications

Khorami, Ata; Saeidi, Roghayeh; Sachdev, Manoj; Sharifkhani, Mohammad

doi:10.1016/j.vlsi.2019.07.001

Cited by 27 publications

(19 citation statements)

References 28 publications

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“…The design parameters of the proposed comparator were improved as compared to CDTC and comparators which have been proposed in Ref. [21] and refs [1,15,18]. Figure 8 demonstrates the dependency of the proposed comparator delay on various differential input voltages level at different supply voltages.…”

Section: Resultsmentioning

confidence: 99%

“…The inconvenience of the NMOS transistor's source driving V DD À V THN when its gate and drain are biased by V DD is used in the load transistors of the differential amplifier, as an advantage in reducing the output nodes swing of the preamplifier and then F I G U R E 1 6 Monte Carlo results of both the offset voltage (a) and time delay of the proposed dynamic latch comparator (b) for 500 runs (V DD ¼ 1 V, V cm ¼ 0.5 V, ΔV in ¼ 0.5 V, Clk ¼ 20 GHz, C out ¼ 3.8 fF) F I G U R E 1 7 Simulation showing power consumption versus process variations and temperature lowering the power dissipation of the proposed comparator up to 42% of the power dissipation of the conventional comparator and 6% comparing to Ref. [21]. A figure of merit (FOM) must be agreed upon for comparison with previous research works.…”

Section: Resultsmentioning

confidence: 99%

“… Voltage at the preamplifier output nodes during the evaluation phase for both the proposed, conventional and Ref. [21] topologies …”

Section: Proposed Dynamic Latch Comparatormentioning

confidence: 99%

“…, using the NMOS load device would help in lowering the preamplifier power consumption. However, the power consumption of the latch is negligible compared to the power consumption of the preamplifier [21]. Therefore, the total power dissipated in the design can be derived as follow:…”

Section: Power Dissipationmentioning

confidence: 99%

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A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Folla

Crespo

Wembe

et al. 2020

IET Circuits, Devices & Syst

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The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research reports the design and implementation of a low‐offset, low‐power and high‐speed dynamic latch comparator. In this work, an enhanced differential pair amplifier is employed in the preamplifier stage, to improve the power dissipation and the comparison speed of the device. A custom latch structure with rigorous transistor sizing was implemented to avoid short circuit current and mismatch in the module. The effective trans‐conductance of the cross‐coupled transistors of the latch was therefore improved for an optimal time delay solution. The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. Moreover, the core circuit layout occupies only 183.3 μm2.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“… Voltage at the preamplifier output nodes during the evaluation phase for both the proposed, conventional and Ref. [21] topologies …”

Section: Proposed Dynamic Latch Comparatormentioning

confidence: 99%

Section: Power Dissipationmentioning

confidence: 99%

See 2 more Smart Citations

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Folla

Crespo

Wembe

et al. 2020

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

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“…The working process of the quantizer is divided into sampling [ 28 ] and digital conversion. Both of these two processes are completed in the sampling phase (φ1/φ1d) of the integrator.…”

Section: Quantizer Circuit Module Analysis and Optimization Designmentioning

confidence: 99%

A Low Power Sigma-Delta Modulator with Hybrid Architecture

Xia

et al. 2020

Sensors

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Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

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