A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications

Srinivasan, R.; Turker, Didem; Sánchez-Sinencio, E.

doi:10.1109/iscas.2007.378555

Cited by 17 publications

(9 citation statements)

References 8 publications

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“…In [1], the authors adopt hybrid technique to achieve a locking time of 20 us, but at the expenses of a high power consumption of 29.6 mW and a chip area of 2.08 mm 2 . Literature [2] uses a low power technique to reduce power consumption, but suffers from long locking time of 55 us. A low voltage design to reduce power consumption is published and attractive, but with a bigger chip area of 1.68 mm 2 [3].…”

Section: Introductionmentioning

confidence: 99%

A 2.4-GHz Fractional-N PLL Frequency Synthesizer with a Low Power Full-Modulus-Range Programmable Frequency Divider

Huang

Yang

2013

Internet and Distributed Computing Systems

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A low-phase noise fractional-N PLL (phase-locked loop) frequency synthesizer operating at 2.4 GHz band is fabricated in TSMC 0.18-um CMOS process. The proposed prototype with a ΣΔ MASH 1-1-1 modulator and a fullmodulus-range programmable frequency divider of static D-flip-flop-based (DFF based) divider cells to reduce both power consumption and phase noise features high programmability, full modulus range, smaller area, and good phase noise. At 1.8 V supply voltage, measured results achieve a wide tuning range from 2.11 to 2.42 GHz, corresponding to 13.7%, a phase noise of -107.4 dBc/Hz at 1 MHz offset from 2.36 GHz, a power consumption of 21.3 mW and an output power of -9.93 dBm. Including pads, the chip area only occupies 0.744 mm 2 .

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Section: Introductionmentioning

confidence: 99%

A 2.4-GHz Fractional-N PLL Frequency Synthesizer with a Low Power Full-Modulus-Range Programmable Frequency Divider

Huang

Yang

2013

Internet and Distributed Computing Systems

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“…Phase‐locked loop (PLL) is a critical component used in a RF wireless receiver. Numerous designs of 2.4 GHz PLLs are found in standard CMOS process and performed much growth in recent years [1–3]. In Ref.…”

Section: Introductionmentioning

confidence: 99%

“…1, the authors adopt hybrid technique to achieve a locking time of 20 μs, but at the expenses of a high power consumption of 29.6 mW and a chip area of 2.08 mm 2 . Literature [2] uses a low power technique to reduce power consumption, but suffers from long locking time of 55 μs. A low voltage design to reduce power consumption is published and attractive, but with a degraded phase noise of −110.5 dBc/Hz and with a bigger chip area of 1.68 mm 2 [3].…”

Section: Introductionmentioning

confidence: 99%

A low‐chip area and low‐phase noise hybrid phase‐locked loop

Huang

Hsu

Chen³

2012

Micro & Optical Tech Letters

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A low‐chip area and low‐phase noise phase‐locked loop (PLL) combining fractional‐N and integer‐N modes operating at 2.4 GHz band is proposed and fabricated in TSMC 0.18‐μm CMOS process.The proposed PLL with a Gm‐boosted Colpitts voltage‐controlled oscillator improves phase noise and a hybrid design of different divider loops achieves fast lock. At 1.8 V supply voltage, the proposed PLL shows a wide tuning range from 2.14 to 2.36 GHz, corresponding to 9.7%, a phase noise of −119.3 dBc/Hz at an offset frequency of 1 MHz from the carrier frequency of 2.14 GHz, a power consumption of 17.3 mW, and an output power of −15.37 dBm. Including pads, the chip area only occupies 0.588 (0.87 × 0.67) mm2. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2295–2300, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27082

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“…The frequency synthesizer reported in [4] proposes a new spur suppression technique, but consumes a power of 18 mW. Reference [5] provides a synthesizer for IEEE 802.15.4/Zigbee applications consumes a power of 15 mW in 0.18 um CMOS technology. For the popular transceiver's architecture shown in Fig.1 with direct upconversion for the TX and low IF down-conversion, the synthesizer needs to generate LO outputs having both I-Q outputs.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Krishna

Xie

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 uW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122dBc/Hz at 1 MHz offset. IntroductionMost of the wireless communication standards prior to IEEE 802.15.4/Zigbee were tailored towards high data rate and multimedia friendly applications. The need for low data rate and low power wireless solutions with emphasis on sensor network applications resulted in the development of IEEE 802.15.4 standard. The recent development and advanced scaling CMOS technologies have made it more attractive to implement a single chip CMOS wireless transceiver featuring both high level of integration and low power consumption [1]. The higher power consumption in the frequency synthesizer is mainly due to the VCO and the first stage divider which is driven by the VCO. The 2.4 GHz synthesizer reported in [2] with a frequency resolution of 5 MHz consumes a power of 7.85 mW at 1.8 V power supply in 0.18 um CMOS technology. Here, the first stage divider is designed using current-mode logic (CML) [6] which consumes a large amount of power. The synthesizer reported in [3] consumes 2.4 mW at 1.2 V supply in 0.13 um CMOS technology. It uses a 16/17 dynamic logic prescaler as first stage divider which consumes only 176 uA at 2.5 GHz and the complete divider is designed with 5

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A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications

Cited by 17 publications

References 8 publications

A 2.4-GHz Fractional-N PLL Frequency Synthesizer with a Low Power Full-Modulus-Range Programmable Frequency Divider

A 2.4-GHz Fractional-N PLL Frequency Synthesizer with a Low Power Full-Modulus-Range Programmable Frequency Divider

A low‐chip area and low‐phase noise hybrid phase‐locked loop

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

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