A low power memory cell design for SEU protection against radiation effects

Shiyanovskii, Yuriy; Rajendran, Aravind; Papachristou, C.

doi:10.1109/ahs.2012.6268665

Cited by 15 publications

(26 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To tolerate SEUs and/or even DNUs, researchers have proposed a series of latches, flip-flops, and memory cells. The designs in [4]- [7] consider hardening for flipflops, the designs in [8]- [16] consider hardening for latches, while the other designs in [17]- [26] and the designs proposed in this paper consider hardening for memory cells. The traditional memory cell is called 6T, which consists of six transistors, i.e., two PMOS and two NMOS transistors for retaining values, and two extra NMOS transistors for access operations.…”

Section: Introductionmentioning

confidence: 99%

“…Since the 6T cell cannot tolerate SEUs, many radiation hardened memory cells have been proposed to improve robustness. Typical SEU and/or even DNU hardened cells include NASA13T [17], Lin12T [18], RHD12T [19], RH12T [20], QUCCE10T [21], and QUCCE12T [21]. However, these memory cells still have the following problems.…”

Section: Introductionmentioning

confidence: 99%

“…(1) Most of the existing memory cells suffer from a large silicon area and power dissipation, such as NASA13T [17], Lin12T [18], and RH12T [20]. Moreover, some cells suffer from a large read and write access time, such as NASA13T [17] and QUCCE10T [21].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Yan

Zhou

et al. 2019

IEEE Access

View full text Add to dashboard Cite

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Yan

Zhou

et al. 2019

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Indeed, when the supply voltage is reduced, soft error rate (SER) increases substantially due to critical charge Q crit reduction [9], [10] where Q crit is the minimum amount of charge collected by a node that is able to flip the state of an affected memory cell. Soft errors during reads can also be a concern, since the Q crit can diminish due to the interference of the precharged bit lines [11]. In addition, memory robustness to noise decreases due to static noise margin (SNM) reduction in drowsy modes [12].…”

Section: Introductionmentioning

confidence: 99%

“…It has been shown that, both during stand-by and reads, the Q crit and SNM degrade considerably due to BTI aging [11]. In [12], the negative effect of BTI on memory reliability has been considered for the selection of the minimum voltage that guarantees high reliable data retention in low-power memories.…”

Section: Introductionmentioning

confidence: 99%

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

Rossi

Tenentes

Reddy

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Bai,

Chen,

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryAs the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations.

show abstract

A low power memory cell design for SEU protection against radiation effects

Cited by 15 publications

References 10 publications

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Contact Info

Product

Resources

About