Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Abstract

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

“…For the above simulations of the proposed SESRS cell, a flexible double-exponential current-source model was used to perform all fault injections. The time constant of the rise and fall of the current pulse was set to 0.1 and 3.0 ps, respectively [21]. The injected charge was up to 25fC.…”

“…, , a a a an a a a an an n n n n n n n n nd d qi q qi qi qi q q q q qi i i q q q qi i i q q q q q q q q q q n n ng n n n n ng g g ng g g n n n n n ng g g g g g n n n ng g g g g g g g g g g g g g g g W W W e e en n n n e e e e en n n e e en n e e e 4 solutions increase the area overhead and design complexity. Our previously proposed SRAM cell in [21] still suffers from the problem that it cannot provide complete self-recoverability from SNUs although it has small overhead. Based on the RHBD approach, this paper presents a highly reliable SRAM cell with improved self-recoverability from soft errors.…”

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

“…Regarding previous works, the SRAM cell in [23] suffers from large overhead. More than one node in the cell in [24] cannot self-recover from SNUs. The SRAM cell in [25] has only four DNU-recoverable pairs of nodes.…”

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications

“…latches, flip-flops, and SRAMs have been proposed by researchers to tolerate/mitigate SNUs and/or DNUs [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Typical designs about SRAMs include NASA13T [18], RHD12T [19], QCCM12T [20], QUCCE12T [21], DNUSRM [22], we-Quatro [23], Zhang14T [24], and QCCM10T [20]. However, these SRAMs still have the following problems.…”

“…(1) Most SRAM cells can achieve self-recovery from SNUs, but they have high power consumption and large silicon area, such as NASA13T [18], RHD12T [19], QCCM12T [20], QUCCE12T [21], DNUSRM [22], and we-Quatro [23]. Moreover, some cells have a large read and write access time, such as NASA13T [18] and QUCCE10T [21].…”