A low-power SRAM design with enhanced stability and I
            <sub>ON</sub>
            /I
            <sub>OFF</sub>
            ratio in FinFET technology for wearable device applications

Abbasian, Erfan; Birla, Shilpi; Sachdeva, Ashish; Elangovan, M.

doi:10.1080/00207217.2023.2238326

Cited by 7 publications

(1 citation statement)

References 38 publications

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“…The FinFET technology offers better gate control and higher 'on' current compared to CMOS devices. Moreover, better electrostatic control in multi-gate FinFET devices has more impact on digital circuitry, such as SRAM structures [8]. However, the current FinFET research indicates that the subthreshold slope (SS) shows a rising stretch with scaling, despite ITRS Roadmap predictions [9].…”

Section: Introductionmentioning

confidence: 99%

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Sachdeva,

Sharma,

Bhargava

et al. 2024

Phys. Scr.

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Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read-and-hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21× and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99× compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

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Section: Introductionmentioning

confidence: 99%

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Sachdeva,

Sharma,

Bhargava

et al. 2024

Phys. Scr.

Self Cite

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Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

Juneja,

Elangovan,

Sharma

2024

Int J Numerical Modelling

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The error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

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A FinFET‐Based Low‐Power Static Random Access Memory Cell With Improved Stability

Rana,

Sachdeva,

Elangovan

et al. 2024

Int J Numerical Modelling

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This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits, i.e., 6T, read‐decoupled 8T(8TRD), Schmitt‐trigger based 10T (10TST), and Schmitt‐trigger‐based modified 10 T (10TMST). The write power in proposed design is reduced by 1.36×/1.32×/1.88×/1.47× compared to 6T/8TRD/10TST/10TMST cells. The write and read stability of proposed design is improved by 1.15×/1.86×/1.28×/1.148× and 2.27×/1×/1.57×/1.11×, respectively. The proposed design also shows the low variability compared to other SRAM bit‐cells.

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A low-power SRAM design with enhanced stability and I _ON /I _OFF ratio in FinFET technology for wearable device applications

Cited by 7 publications

References 38 publications

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

A FinFET‐Based Low‐Power Static Random Access Memory Cell With Improved Stability

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A low-power SRAM design with enhanced stability and I ON /I OFF ratio in FinFET technology for wearable device applications

Cited by 7 publications

References 38 publications

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

A FinFET‐Based Low‐Power Static Random Access Memory Cell With Improved Stability

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A low-power SRAM design with enhanced stability and I _ON /I _OFF ratio in FinFET technology for wearable device applications