A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme

Fukushi, I.; Sasagawa, R.; Hamaminato, Makoto; Izawa, T.; Kawashima, Seiichiro

doi:10.1109/vlsic.1998.688039

Cited by 16 publications

(6 citation statements)

References 6 publications

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“…Compared with latch-type SAs, the charge-transfer amplifier overcomes the V th relative difference between the pair MOS transistors, and thus reduces the input offset voltage. Subsequently, some modified charge-transfer SAs based on the BCTSA are presented for high-performance and low-power solution [14,23,38]. However, the charge-transfer SAs usually require an extra intermediate voltage, which is difficult to realize in digital systems.…”

Section: Voltage-mode Sense Amplifiersmentioning

confidence: 99%

“…The charge-transfer SA was proposed in 1976, which consists of a pair of NMOS transistors [13]. Subsequently, several SA designs have been proposed utilizing the same charge-transfer mechanism [14][15][16], all of which exhibit a fast response speed, almost independent of the bit line capacitance. However, the charge-transfer SA usually requires an intermediate voltage and complicated control signals increasing the additional area and energy.…”

Section: Introductionmentioning

confidence: 99%

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Review of Sense Amplifiers for Static Random Access Memory

Zhu¹,

Bai²,

Wu³

2013

IETE Tech Rev

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Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs). This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM. Recent advances in developing SAs have paved the way for lower delay, lower energy, and higher reliability. For comparison, all SAs based on 65 nm CMOS technology are simulated under different power supplies, bit-line capacitances, and various process corners. When the bit-line capacitance is 50 fF, charge-transfer and current-mode SAs are about 40% faster than voltage-mode SAs, and the energy consumption of charge-transfer SA is 30% lower than that of other voltage-mode SAs. Delay and energy of HCI-trimming SA and multi-sized SA are about equal to that of voltage-mode SAs. Because of low bit-line precharged voltage, the energy of charge-limited sequential SA (CLSSA) is 64% lower than that of charge-transfer SA, while the delay of CLSSA is five times larger than the other SAs. AUTHORSJiafeng Zhu received the M.S. degree from Southeast University, China, in 2010 in electronic engineering. He is currently a Ph.D. candidate in National ASIC System Engineering Research Center, Southeast University, China. His research interests include high performance and low power SRAM design and mix-signal IC design.

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Section: Voltage-mode Sense Amplifiersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Review of Sense Amplifiers for Static Random Access Memory

Zhu¹,

Bai²,

Wu³

2013

IETE Tech Rev

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“…A difference in V T of 0.1 V reduces the standby subthreshold current to one-fifth its value for a single low V T , although an excessive V T difference might cause a race condition problem between low-and high-V T circuits. The dual-V T scheme is also applied to SRAMs [54,56]. It was reported that a combination of dual V T and dual V DD achieved a high-speed low-power 1-V e-SRAM [56].…”

Section: Figure 14mentioning

confidence: 99%

“…The dual-V T scheme is also applied to SRAMs [54,56]. It was reported that a combination of dual V T and dual V DD achieved a high-speed low-power 1-V e-SRAM [56]. Another application of the dual-V T scheme is a high-V T power switch [12, 14 -18] that can cut the subthreshold current of an internal low-V T core in standby mode, as described in the subsection on circuit applications.…”

Section: Figure 14mentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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“…In a DRAM [9] multi-V T can easily be produced by applying internal supply voltages (lowered and raised from V DD ) generated by onchip voltage converters. A combination of dual V T and dual V DD has also been proposed for making a 1-V e-SRAM [34]. Power Switch: A high-V T PMOST power switch [9], applied to a low-V T internal core, completely cuts the subthreshold current from the core by turning off the switch in standby mode.…”

Section: Standby Modementioning

confidence: 99%

Low-voltage memories for power-aware systems

Itoh¹

Proceedings of the International Symposium on Low Power Electronics and Design

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This paper describes low-voltage RAM designs for stand-alone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction.First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing. Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active-mode leakage currents, and memory-rich SOC architectures.

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A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme

Cited by 16 publications

References 6 publications

Review of Sense Amplifiers for Static Random Access Memory

Review of Sense Amplifiers for Static Random Access Memory

Review and future prospects of low-voltage RAM circuits

Low-voltage memories for power-aware systems

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