This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K 2 2 2 16-b SRAM fabricated in a 0.25-m dual-Vt Vt Vt CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes.

In this paper we propose an improved version of the charge transfer sense amplifier (CT sense amp) which completely compensates the threshold voltage (Vth) difference of MOS FETs.We also present a dual-Vth CMOS circuit scheme that enables high speed operation and low leakage power consumption at low supply voltage. A low-power, low-voltage 2k x 16b SRAM macro was designed and fabricated using a 0.25pm process. It showed stable operation with an access time of 7.0ns and power consumption of 3.9mW at 1 .OV (boost 1 SV), 100MHz, 85°C.

No abstract

The two dominant methods of reducing SRAM power have been to reduce operating range and to limit signal swings on the highcapacitance bit and I/O lines [l]. As a consequence, decode and write now consume a significant fraction of SFWM power. DualVt CMOS circuit techniques implement reduced-swing decode and write [l]. Swings on high-capacitance predecode lines, bitlines and write bus, are limited to half Vdd. The half-Vdd supply is generated internally with high efficiency by chargerecycling between positive and negative half-swing signals. SRAM architecture and decoder organization are shown in Figure 1. The main limitation resulting from reducing signal swings is reduction in gate overdrive at the receiving transistor leading to delay penalty. This design overcomes this using positive and negative half-swing signals on high-capacitance predecode lines so active decode circuits see a full gate-overdrive, while reducing decoder power. The half-Vdd supply is generated internally with high efficiency using charge-recycling between positive and negative half-swing signals.SRAM architecture and decoder organization are shown in Figure 1. Predecoder delay is further reduced using pulse-mode self-resetting gates ( Figure 2). The circuits are similar to the self-resetting gate introduced in Reference 2, except for the final stages that are either supplied with VddI2 and Vdd to create a positive half-swing pulse, or VddI2 and Gnd to create a negative half-swing pulse. The row decoder and the block decoder AND the predecoded half-swing signals using a static CMOS NAND that merges the voltage level conversion (from half-swing to full-swing) with a logical AND (Figure 3a) [31. The nMOS pull-down stack made up of high-Vt transistors is followed by an inverter with a PMOS leaker feedback transistor. The two gate inputs are driven by positive half-swing pulses, while the source terminal of the stack is used as an input for the negative half-swing pulse. In the select condition, all nMOS transistors have the full gate overdrive ( Figure 3a). Low Vt PMOS pullups are used since they have only half-Vdd gate overdrive when none of the gate inputs are active ( Figure 3b). The limitation of this circuit is the reduced noise margin in the half-select cases (Figure 3c,d) where the nMOS transistors end up with half-Vdd gate-to-source voltage. But since the threshold of the high-Vt nMOS is close to half-Vdd, these transistors are only weakly turned on. A PMOS leaker is employed to further improve noise margin. By limiting Vdd to around 2Vt, robust gate operation is achieved. Given the small noise margins on half-swing gates, where possible, positive and negative half-swing signals are interleaved to reduce noise coupling onto the inactive half-swing lines (qs, os, re and we in Figure 1). The 8-signal predecode buses, rsl and rs2, that carry one active positive half-swing pulse, are twisted to reduce noise coupling by a factor of four (Figure 1).To limit write power, the bitline precharge reference is Vdd/2. During writes the bitline swiii...

No abstract