A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

Hosseini, Seyed Rasool; Saberi, Mehdi; Lotfi, Reza

doi:10.1109/tcsii.2014.2345295

Cited by 79 publications

(57 citation statements)

References 7 publications

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“…Similarly, the achieved power dissipation in this research is slightly lower while the output delay is approximately 19×10 6 times smaller. Only the level shifter circuit presented in [21] consumes approximately 0.015 nW power less than the proposed level shifter which is a very insignificant amount. Nevertheless, the proposed level shifter circuit is approximately 1330 times faster compared to the level shifter circuit presented in [21].…”

Section: Resultsmentioning

confidence: 97%

“…Only the level shifter circuit presented in [21] consumes approximately 0.015 nW power less than the proposed level shifter which is a very insignificant amount. Nevertheless, the proposed level shifter circuit is approximately 1330 times faster compared to the level shifter circuit presented in [21]. Thus, from this comparison, it is evident that the designed level shifter circuit in this research marks a significant improvement in terms of operation speed and power dissipation of level shifter circuits.…”

Section: Resultsmentioning

confidence: 97%

“…Moreover, it has a negative impact on overall power consumption. To address the design issue, few other designs are presented in the literature [18][19][20][21][22]. Among these solutions, level shifter circuits designed in [18,19,21] depend on the difference of voltage supply.…”

Section: Introductionmentioning

confidence: 99%

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Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

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Section: Resultsmentioning

confidence: 97%

Section: Resultsmentioning

confidence: 97%

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Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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show abstract

“…Osaki et al used the current generators (CGs) which turn ON only when the input and output logic level differs [13]. Contention problem of [13] is discussed in [14], where they proposed a new design based on CGs and solved the problem through output feedback. Their design uses 14 transistors, and proper sizing is required to charge the internal nodes and reduce the power dissipations of the inverter (output of which is fed back to the CGs).…”

Section: Introductionmentioning

confidence: 99%

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load. ARTICLE HISTORY

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“…An LS with logic-error correction (LSLEC), proposed in [8], uses the current generators (CGs) that supply current when the logic level of the output is not corresponding to the logic level of the input. Contention problem of LSLEC is discussed in [9] where they propose a new LS using CGs and solve the problem by feeding back the output signal. However, their design (without an inverter) is based on 12 transistors, and proper sizing is required to charge the internal nodes and reduce the power dissipations of the inverter (output of which is fed back to the CGs).…”

Section: Introductionmentioning

confidence: 99%

Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

IEICE Electron. Express

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Level shifter circuits are necessary parts of modern SoCs, as they interface different voltage domain signals. This paper presents an energyefficient level up shifter capable of converting sub-threshold input signal to higher levels. The proposed design uses the feedback mechanism of a regulated gate cascode to achieve energy efficient operation. Once the desired output level is achieved, large static current does not flow, and static power is further minimized using a transistor stack. Implementing in a 90-nm process, post-layout simulation results show that the proposed level shifter has a propagation delay of 21.2 ns, a total energy-per-transition of only 77.5 fJ, and a static power dissipation of 7.2 nW.

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A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter

Cited by 79 publications

References 7 publications

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

Energy efficient low static-power voltage level shifter

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