Proceedings 18th IEEE VLSI Test Symposium
DOI: 10.1109/vtest.2000.843865
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A low-speed BIST framework for high-performance circuit testing

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Cited by 6 publications
(3 citation statements)
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“…First the basic principles of a controllable-delay flip-flop will be shown as this type of flip-flop forms the basis of our DfDT structure. The detail description of the behaviour and usage of controllable-delay flip-flops in a system environment can be found in [4,11]. …”
Section: The Detection Of Delay Faultsmentioning
confidence: 99%
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“…First the basic principles of a controllable-delay flip-flop will be shown as this type of flip-flop forms the basis of our DfDT structure. The detail description of the behaviour and usage of controllable-delay flip-flops in a system environment can be found in [4,11]. …”
Section: The Detection Of Delay Faultsmentioning
confidence: 99%
“…This architecture and its components have been described in detail and simulated in VHDL at system level and using HSPICE data for different blocks in previous work [3,4]. In this paper, the complete architecture has been simulated at circuit level, making use of HSPICE and using the 0.35 pm TSMC CMOS technology from MOSIS [12].…”
Section: The Dfdt Structure Usedmentioning
confidence: 99%
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