A manufacturing perspective of wafer level CSP

Nguyen, Luu; Kelkar, N.; Takiar, Hem

doi:10.1109/ectc.2000.853126

Cited by 11 publications

(4 citation statements)

References 3 publications

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“…There are more than 30 different types of WLCSP reported in the literature, and their advantages and disadvantages have already been discussed. [1][2][3][4] Just like many other new technologies, however, WLCSP still faces many critical issues (only solder-bumped WLCSP will be considered [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] ):…”

Section: Microvia and Wafer-level Chip-scale Package (Wlcsp)mentioning

confidence: 99%

Microvias for Low Cost High Density Interconnects

2003

Circuit World

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All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps.McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. For more information, please contact George Hoare, Special Sales, at

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Section: Microvia and Wafer-level Chip-scale Package (Wlcsp)mentioning

confidence: 99%

Microvias for Low Cost High Density Interconnects

2003

Circuit World

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“…In addition the surface of the wafer is encapsulated in low stress epoxy, exposing only the top portions of the posts where the solder balls will be attached. The redistribution layer, which is developed on the dielectric polymer layer, also improves chip reliability by allowing the use of larger and more robust solder balls for interconnection [5][6][7][8][9][10][11][12][13][14][15][16]. In the current development of WLCSP, 6' wafer is used.…”

Section: Introductionmentioning

confidence: 99%

Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)

Gao¹,

Hong²,

Kim³

et al. 2008

2008 2nd Electronics Systemintegration Technology Conference

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In this study a WLCSP structure in microelectronic application is considered. In the current development of WLCSP solder post is used to bridge the die and solder bump to release part of the stress concentration caused by mismatch of Thermal Expansion Coefficient (CTE). Thermal cycle reliability analysis on solder joints with 3D finite element simulation is firstly carried out. The stress/creep strain distribution and evolution are analyzed and the fatigue lives of solder joints are estimated. Finite element model is also verified and the fatigue property of currently used solder is determined with JEDEC thermal cycle reliability test. Structure design optimization is thereafter performed to improve the reliability of WLCSP. Parametric studies on the geometry structures are carried out, such as die thickness, solder post height and solder bump diameter, etc. The results show that solder post does great help to improve the solder bumps' reliability, the height of which plays an important role in controlling the fatigue life of the package. Higher post helps to release the stress concentration and therefore extend the fatigue life of solder bumps. In addition, die thickness plays the most important role in affecting fatigue life of solder joints. The thinner the die, the better the reliability of WLCSP is. Other parameters, such as the diameter of the solder bump, only have tiny effect on the solder joints reliability ofWLCSP.

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“…In the past few years the research and development for wafer level chip scale packages (WLCSP) has become one of the most‐discussed issues in the IC packaging industry (Garrou, 2000; Nguyen et al ., 2000; Topper et al ., 2000; Ahn et al ., 2000; Mirza, 2000; Simon and Reichl, 2000; Teutsch et al ., 2000; Tong et al ., 2000; Lau et al ., 2000a,b; Lau et al ., 1999; Jim et al ., 1999; Lau, 2000a,b; Lau and Lee, 1999; Lau et al ., 1998). This is a direct result of massive demands for packages with higher performance and lower cost.…”

Section: Introductionmentioning

confidence: 99%

Analysis and comparison of WLCSP‐on‐build‐up PCB assemblies with various solders and microvia configurations

Lee

Lau

2002

Circuit World

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In this paper, a computational analysis is presented for the comparison of wafer level chip scale package‐on‐build‐up PCB assemblies with various solders and microvia configurations. The printed circuit board of the assembly has one build‐up layer on one side. For comparison, the board with two build‐up layers on the same side is studied as well. Furthermore, two solder joint materials, namely, 62Sn–2Ag–36Pb and 96.5Sn–3.5Ag are studied for comparison. The assembly is simulated by a finite element model and the model is analyzed under thermal cyclic loading. A comprehensive stress analysis is performed and comparisons are made for assembly deformation, stress/strain ranges, and creep responses.

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A manufacturing perspective of wafer level CSP

Cited by 11 publications

References 3 publications

Microvias for Low Cost High Density Interconnects

Microvias for Low Cost High Density Interconnects

Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)

Analysis and comparison of WLCSP‐on‐build‐up PCB assemblies with various solders and microvia configurations

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