A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Abstract

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si,NI, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

Research progresses of dynamic random access memory devices

“…同样, 考虑到10 s以上的数据保持时间, 阵列访问 晶体管的关态漏电流应低于1 fA [3] . 通常可以通过负 韩国的DRAM厂商随后也使用了类似的晶体管 [8][9][10][11] . 凌发明的BWL技术进行大规模生产, 包括三星电子的 20 nm存储器芯片, 也使用了BWL技术 [12] .…”

A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors

“…Two approaches have been employed to overcome this obstacle: increasing the surface area ( A ) and increasing the dielectric constant ( k ) of the storage capacitor. For the first approach, storage capacitors are converted from planar into three-dimensional (3D) structures to maximize their aspect ratios [3]. Regarding the second approach, various types of high- k materials are introduced such as ZrO 2 [4], TiO 2 [5], and SrTiO [6], which tends to deteriorate the defect density and bandgap energy [7].…”

Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

“…The scaling-down of dynamic random access memory (DRAM) cells is the key engineering factor to achieve higher integration density, lower power consumption and higher operation speed [1][2][3]. It has been reported that scaling-down below the half-pitch size of 20 nm would be the physical limit of the conventional memory cell structure, consisting of one n-metal-oxide-semiconductor field-effect transistor (n-MOSFET) and one cylindrical capacitor, because the capacitors of the DRAM cells would collapse on one another [4][5][6][7][8]. The capacitor-less memory cell is a promising candidate to overcome the limitation of the conventional DRAM cell structure, being produced by just one n-MOSFET fabricated on a silicon-on-insulator (SOI) substrate and performing volatile memory cell operation [9][10][11]17].…”