A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-Gate MOSFETs

Netsu, Seiko; Hellenbrand, Markus; Zota, Cezar B.; Miyamoto, Yasuyuki; Lind, Erik

doi:10.1109/jeds.2018.2806487

Cited by 7 publications

(1 citation statement)

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“…The most promising new technology is a combination of a high-k oxide and III-V channel materials because of outstanding carrier transport properties such as the effective electron mobility (µ n ) and injection velocity (ν x0 ) [1][2][3][4][5][6]. For the past three decades, a key bottleneck in developing III-V MOSFETs has been poor interface state quality between the oxide and III-V channel [7][8][9][10][11]. Atomic-layer-deposition (ALD) provides a very good quality interface, presumably due to the "self-cleaning effect" during the high-k deposition, especially in the In 0.53 Ga 0.47 As channel [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

Kim

2019

Electronics

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We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

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