Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

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1  Abstract-We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb Tunneling Field-Effect Transistors integrated on Si substrates. The best subthreshold swing, 68 mV/dec at VDS = 0.3 V, was achieved for a device with 20 nm InAs diameter. The on-current for the same device was 35 µA/µm at VGS = 0.5 V and VDS = 0.5 V. The fabrication technique used allow downscaling of the InAs diameter down to 11 nm with a flexible gate placement.

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