A method of computation for worst-case delay analysis on SpaceWire networks

Ferrandiz, Thomas; Frances, Fabrice; Fraboul, Christian

doi:10.1109/sies.2009.5196187

Cited by 35 publications

(55 citation statements)

References 5 publications

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“…In this work, we focus on Round Robin (RR) arbitrated NoC architectures as this is the arbitration mechanism implemented on the Kalray MPPA R [8]. Ferrandiz et al [17] propose the Recursive Calculus (RC) method for RR arbitrated NoCs. The RC takes the largest possible interference of contending flows on each link into account and calculates a safe WCTT for individual NoC packets.…”

Section: Related Workmentioning

confidence: 99%

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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms.In this work, we target a state-of-the-art many-core processor, the Kalray MPPA. A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis. Abstract-Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip (NoC), which is used for communication among the compute cores via the off-chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. Partitioning and Analysis of theIn this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

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Section: Related Workmentioning

confidence: 99%

“…The number of interfering messages, the payload size of the messages, the routing, as well as the arbitration protocol implemented by the NoC routers affect the blocking delay that a message may incur [17].…”

Section: B Interfering Messages On the Nocmentioning

confidence: 99%

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…To verify if the given time requirements can be satisfied, suitable schedulability tests are necessary during the design phase of a real-time system. Methods to compute the end-to-end latency of a packet in round-robin arbitrated NoCs have been presented in Ferrandiz et al (2009), Dasari et al (2014. Targeting fixed-priority based NoCs, the authors in Burns (2008, 2009a, b) present a Response Time Analysis (RTA) based on the well-known analysis for task scheduling (Joseph and Pandya 1986).…”

Section: Related Workmentioning

confidence: 99%

Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NoCs

et al. 2017

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Network-on-Chip (NoC) is a preferred communication medium for massively parallel platforms. Fixed-priority based scheduling using virtual-channels is one of the promising solutions to support real-time traffic in on-chip networks. Most of the existing works regarding priority-based NoCs use a flit-level preemptive scheduling. Under such a mechanism, preemptions can only happen between the transmissions of successive flits but not during the transmission of a single flit. In this paper, we present a modified framework where the non-preemptive region of each NoC packet increases from a single flit. Using the proposed approach, the response times of certain traffic flows can be reduced, which can thus improve the schedulability of the whole network. As a result, the utilization of NoCs can be improved by admitting more real-time traffic. Schedulability tests regarding the proposed framework are presented along with the proof of the correctness. Additionally, we also propose a path modification approach on top of the non-preemptive region based method to further improve schedulability. A number of experiments have been performed to evaluate the proposed solutions, where we can observe significant improvement on schedulability compared to the original flit-level preemptive NoCs.This work is an extended version of the paper presented at RTCSA 2016 (Liu et al. 2016).

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“…Several methods have been proposed to obtain upper-bounds on worst-case latencies ( [8], [10], [11]), but they yield either pessimistic results [10], [11], or have complexity and scalability issues [8]. Conversely, if a platform contains multiple virtual channels ( [6], [7]), the benefits are twofold: (i) by avoiding idle routers, the performance of the wormhole switching technique is significantly improved ( [6], [7]) and (ii) preemptions can be implemented [24].…”

Section: Related Workmentioning

confidence: 99%

Worst-case memory traffic analysis for many-cores using a limited migrative model

Nikolic

Yomsi

Petters

2013

2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications

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The ratio between the number of cores and memory subsystems (i.e. banks and controllers) in many-core platforms is constantly increasing, leading to non-negligible latencies of memory operations. Thus, in order to study the worst-case execution time of an application, it is no longer sufficient to only take into account its computational requirements, but also have to be considered latencies related to its memory operations.In this paper we study a limited migrative model applied upon many-core platforms. This approach is based on a multi-kernel paradigm [3] -a promising step towards scalable and predictable many-cores, which are essential prerequisites for the integration of such systems into the real-time embedded domain. Under that assumption, we present two analytical methods to obtain the worst-case memory traffic delays of individual applications. Through experiments we test the applicability of the proposed approaches to different scenarios, and draw practical conclusions concerning routing mechanisms and a distribution of memory operations across memory controllers.

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A method of computation for worst-case delay analysis on SpaceWire networks

Cited by 35 publications

References 5 publications

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Using non-preemptive regions and path modification to improve schedulability of real-time traffic over priority-based NoCs

Worst-case memory traffic analysis for many-cores using a limited migrative model

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