A Methodical Approach to Hybrid PLL Design for High-Speed Wireless Communications

Linn, Y.

doi:10.1109/wamicon.2006.351927

Search citation statements

Order By: Relevance

Paper Sections

Select...

Types Of Jitter1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2008

2014

Publication Types

Select...

Article3

Other3

Relationship

Self Cite0

Independent6

Authors

Journals

Cited by 10 publications

(1 citation statement)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They generate output transitions not as a result of transitions at their inputs, but rather as a result of the previous output transition. 6 The jitter produced by these blocks is referred to as accumulating jitter; it is a variation in the delay between an output transition and the subsequent output transition.…”

Section: Types Of Jittermentioning

confidence: 99%

Predicting the Jitter of Pll–dll Based Frequency Synthesizers

Patel¹,

Sharma

2014

Int. J. Wavelets Multiresolut Inf. Process.

View full text Add to dashboard Cite

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

show abstract

Section: Types Of Jittermentioning

confidence: 99%