A methodolgy for characterizing cell testability

In given paper the approach for increasing reliability of VLSI circuits by probabilistic-based defect/fault characterization of standard cells is considered. Proposed approach is based on careful defect/fault analysis of complex gates from industrial cell library. Cell characterization includes probabilistic analysis of physical defects (including latent defects), identification of complex gates realistic faulty function caused by probable defects, determination of testability and development of recommendations for layout improvement aimed at decreasing of design sensitivity to physical defects.

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A study on the utility of using expected quality level as a design for testability metric

Williams

Ferguson²,

Larrabee³

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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A methodolgy for characterizing cell testability

Cited by 3 publications

References 8 publications

Gate Layout Improvement Aimed at Testability

Gate Layout Improvement Aimed at Testability

Reliability-aimed defect/fault characterization of standard cells of VLSI circuits

A study on the utility of using expected quality level as a design for testability metric

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