A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks

Obaidat, Mohammad S.; Teng, Jun

doi:10.1016/s0140-3664(99)00008-0

Cited by 4 publications

(4 citation statements)

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“…If b p shows the bit error rate (BER) and f N shows the byte length of FSC, to realize the exact match between received signal and FSC, computing formula of LSR is given as follows [9]:…”

Section: Frame Synchronizationmentioning

confidence: 99%

Co-design of frame synchronization and reed-solomon code based on 8b10b

Haishan

Jia

2009

2009 First International Conference on Networked Digital Technologies

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The large-scale seismic data acquisition system (LSDAS) is a kind of field data acquisition system in super scale. It covers hundreds of square kilometers, so data transmission speed and reliability are the most important criteria. Based on 8b10b modulation code, this paper discusses a co-design method of frame synchronization and error correction code (ECC) at a known bit error rate. The co-design of frame synchronization and ECC can optimize the resources of data transmission system. Generally, decoding of ECC is more complex than frame synchronization, so we should make the error synchronization rate lower than frame error rate after correction as much as possible when designing a system. By this way, the requirement to the performance of ECC becomes lower. Simulation experiments show that data transmission system can be designed more efficiently by using this model.

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“…If b p shows the bit error rate (BER) and f N shows the byte length of FSC, to realize the exact match between received signal and FSC, computing formula of LSR is given as follows [9]:…”

Section: Frame Synchronizationmentioning

confidence: 99%

Co-design of frame synchronization and reed-solomon code based on 8b10b

Haishan

Jia

2009

2009 First International Conference on Networked Digital Technologies

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“…This function is required by the function that calculates the Poisson distribution. 9 float Rngen::ran()(void)&horbar;It calculates a uniformly distributed float between 0.0 and 1.0. 4.…”

Section: The Simulation Modelmentioning

confidence: 99%

“…o void InputQueue::ClearSummary Array (void)-This clears the summary array before processing the cells at the head of each queue. 9 void InputQueue::CreateSummary Array-It fills in the contents of the Summary array after examining the cell at the head of each queue. The summary array is an array of integers and has one entry for each input port.…”

Section: The Simulation Modelmentioning

confidence: 99%

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A Simulation Methodology to Study Input Buffering in ATM Switches

Obaidat

Riehl

1999

SIMULATION

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This paper presents a performance study of input buffering in Asynchronous Transfer Mode switches. The main performance metrics are average cell waiting time and output port contention under a variety of load conditions and operating environments. Results show that as the percent utilization increases, the average cell wait time increases. Analysis of output port contention shows that it increases with the increase in utilization, and the number of conflicts increases with both the utilization and the input queues. The results are presented in a series of curves that present the number of cells delivered during output conflicts versus percent utilization. The software developed offers several benefits: it provides a flexible approach to investigate performance of input queueing under a variety of conditions. The simulation duration, interarrival distribution, number of input queues and maximum queue size can all be varied simply by editing the initialization file; no recompiling of source code is required. It allows for modification and extensibility with only minor software changes. It does not contain operating-specific function calls; thus, it can be used without changes on standard DOS-based PCs or UNIX-based systems.

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10 Gb/s very short reach transmission in parallel optical link

Wang

2007

Electr Eng

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A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks

Cited by 4 publications

References 4 publications

Co-design of frame synchronization and reed-solomon code based on 8b10b

Co-design of frame synchronization and reed-solomon code based on 8b10b

A Simulation Methodology to Study Input Buffering in ATM Switches

10 Gb/s very short reach transmission in parallel optical link

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