A micropower neural recording amplifier with improved noise efficiency factor

Abstract

This article presents a neural recording amplifier suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is the most energy-efficient structure reported to date, which achieves an effective noise efficiency factor (NEF) smaller than the theoretical limit that was claimed in literature for any existing amplifier (NEF=2.02). The proposed technique, which is referred to as partially OTA sharing technique, achieves a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of systematic mismatch on crosstalk between adjacent channels and the trade-off between noise and crosstalk are theoretically analyzed. For an array of four neural amplifiers, simulation results show a midband gain of 39.2 dB and a-3 dB bandwidth from 10 Hz to 10.6 kHz. The input referred noise is simulated to be 2.21 μV rms and the power consumption is 7.92 μW from 1.8 V supply, which refers to NEF=1.8. The worst-case crosstalk within the desired bandwidth is-46.1 dB.

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

“…Assuming large open-loop dc gain for the amplifier (in this design, 72.8 dB), and using the results obtained in (12) for a single diode-connected device, the nonlinear output of the amplifier is approximated as (13) The output voltage is derived by replacing in (13) (14) where (15) Hence, the total harmonic distortion (THD) of the amplifier, which is contributed from the nonlinear diode-connected feedback devices, is expressed as (16) The nonlinear characteristics of the input devices are analyzed using a similar approach. Assuming that are the only sources of nonlinearity, the THD contribution from these devices is obtained as…”

“…MICROPOWER NEURAL AMPLIFIER Fig. 2(a) shows the conventional structure of an array of neural amplifiers, which is adapted from [9] with minor modifications [15]. Diode-connected transistors act as a high value resistors and adjust the high-pass cutoff frequency of the amplifier.…”

Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial

“…The integrated input-referred noise without chopping measured over the bandwidth of 10 Hz to 5 kHz is 5 μV rms (at room tem- perature), which yields a noise efficiency factor of about 7 [33]. For a maximum offset of 50 mV at the input, the input-referred noise goes up to the worst case of 5.4 μV rms .…”

A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

“…This background noise sets the stage for practical neural signal recording. The majority of neural amplifiers that successfully extract in vivo action potentials have an input referred noise value below 3-7 µVrms [1,3,4]. Without this controlled noise level, the signal is drowned in a sea of noise.…”

“…More recently [3,11] reported a power consumption of 7.92 µW and an input referred noise of 3.5 µVrms. Also described is an OTA sharing architecture that effectively reduces both chip area and NEF, which was reported to be 3.…”