A model for gate-oxide breakdown in CMOS inverters

Abstract

The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated. The results show that the inverter performance can be affected by the BD in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide BD conduction has been modeled as gate-to-diffusion leakage with a power-law formula of the type = , which was previously found to describe the BD in capacitor structures. This implies that the BD physics at oxide level is the same as that at circuit level.Index Terms-CMOS, dielectric breakdown, hard breakdown (HBD), leakage currents, oxide breakdown, oxide reliability.

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

“…Extensive research has been conducted on the failure-causing physical phe-nomena, such as electromigration (EM) [22,2] and OBD [6]. The effect of OBD at the circuit level is a shift in the LOW and HIGH voltage values and eventually bit errors for CMOS devices [21,15,16].…”

“…Some recent work [16,15] models the oxide breakdown phenomenon for an inverter using SPICE circuit elements. This work matches the model data to the measured data for the transfer characteristics of the inverter.…”

Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability

“…Soft breakdown increases the gate leakage current noise due to formulation of random defects and conducting path within the oxide [21]. After soft breakdown, the nMOS transistor's threshold voltage is increased [22], [23] due to more trapped charge or defect density in the oxide. The increase in threshold voltage causes a decrease in drain current.…”

Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics

“…Inverter circuit degradation attributed to dielectric wearout or breakdown mechanisms have received recent attention [1][2][3][4][5][6][7][8], yet reports on physical (i.e., not simulated) oxide degradation effects on other logic gates, such as the NAND gate, are minimal. Furthermore, much of the work on inverter reliability has focused on the change of dc voltage transfer characteristics following circuit stressing without investigating the time domain [1,2,7,8].…”

“…Furthermore, much of the work on inverter reliability has focused on the change of dc voltage transfer characteristics following circuit stressing without investigating the time domain [1,2,7,8]. In these studies, individual MOSFETs cannot be examined, so the type and amount of degradation to one or both MOSFETs can only be inferred.…”