A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

Chintaluri, Ashwin; Parihar, Abhinav; Natarajan, Suriyaprakash; Naeimi, Helia; Raychowdhury, Arijit

doi:10.1109/ats.2015.39

Cited by 28 publications

(13 citation statements)

References 11 publications

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“…In this case, the magnetic orientation of the MTJ cells is fixed to a specific configuration so that their magnetic orientation (i.e., resistances) cannot be changed [40]. Note that these defects are sometimes classified in the literature as intracell (within a cell) or intercell (cell-to-cell) defects [41], [42]. Intracell defects refer to resistive opens and shorts on lines inside a cell.…”

Section: ) Strong or Weak Defectsmentioning

confidence: 99%

“…Permanent faults in MRAM can be caused by extreme parametric variations, as described in [43] and [44]. These variations come from changes in both material and lithographic properties, transistor electrical properties, and noise generated by thermal effects [41], [42]. MTJ material parameters that may suffer from variations are magnetic anisotropy, saturation magnetization, TMR ratio, and oxide thickness of the ultrathin insulating layer.…”

Section: ) Strong or Weak Defectsmentioning

confidence: 99%

“…Content is final as presented, with the exception of pagination. Table 3 Typical FFMs in an STT-MRAM [41], [42] expressed as follows:…”

Section: ) Impact Of Process Variationsmentioning

confidence: 99%

“…A detailed description of the nonfunctional behavior associated with each of these FFMs can be found in [39]. As an example, Chintaluri et al [41], [42] have identified FFMs that may occur during read and write operations in an STT-MRAM and how resistive and capacitive defects induce faults. Table 3 summarizes the FFMs and how they contribute to read/write failures.…”

Section: Mram Fault Modelsmentioning

confidence: 99%

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A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

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Section: ) Strong or Weak Defectsmentioning

confidence: 99%

Section: ) Strong or Weak Defectsmentioning

confidence: 99%

“…Content is final as presented, with the exception of pagination. Table 3 Typical FFMs in an STT-MRAM [41], [42] expressed as follows:…”

Section: ) Impact Of Process Variationsmentioning

confidence: 99%

Section: Mram Fault Modelsmentioning

confidence: 99%

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A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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“…The SLS structure also has temporal degradation tolerance characteristic, as the separate circuitry for restoring operation is accessed infrequently. In addition, scaling VDD and the technology nodes induces large process variations [34]- [35], soft errors [36], and manufacturing defects [37] that affect the sensing operation. In this regard, offset cancellation [14]- [15], upset tolerant [38]- [39], and defect tolerant [13] techniques are required to satisfy the stable sensing operation.…”

Section: Introductionmentioning

confidence: 99%

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

Choi

2020

IEEE Access

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In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this paper presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic. INDEX TERMS Auto-zeroing, double sensing margin, dynamic reference voltage (DRV), magnetic tunnel junction (MTJ), near-threshold voltage (NTV), nonvolatile flip-flop (NVFF), sensing inverter variation tolerant (SIVT), sensing margin (SM).

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State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

Cited by 28 publications

References 11 publications

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

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