A Modified Local Density Approximation. Electron Density in Inversion Layers

Al-Ameri

IEEE Trans. Electron Devices

et al. 2015

Abstract-In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

Section: Density Gradient Calibrationmentioning

confidence: 99%

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Al-Ameri

IEEE Trans. Electron Devices

et al. 2015

Applied Physics Letters

“…7 The position of the surface Fermi level, well above the CBM, indicates a downward band bending relative to the Fermi level at the surface, leading to electron accumulation for all wurtzite samples measured. To investigate this further, the band bending profile and corresponding electron accumulation in the surface space-charge region was determined by solving Poisson's equation numerically within the modified Thomas-Fermi approximation ͑MTFA͒ following the method described by Veal et al 17 The MTFA correction has been shown 18 to yield profiles that are in good agreement with those obtained from full self-consistent Poisson-Schrödinger calculations. The resulting profiles are shown in Fig.…”

mentioning

confidence: 99%

Universality of electron accumulation at wurtzite c- and a-plane and zinc-blende InN surfaces

King

Veal

McConville

et al. 2007

104

Solid-State Electronics

“…The gate capacitance was calculated using the Taurus-DAVINCI with a three-dimensional SiNW FET structure. Quantum-mechanical effects were introduced using the modified local density approximation (MLDA) method [22,23]. We used the MLDA method in [22,23] instead of an improved method described in the appendix of [22] because of shorter calculation time of the prior method.…”

Section: Computer Simulation Proceduresmentioning

confidence: 99%

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Sato

Kakushima

Ahmet

et al. 2011

Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. <100>-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100 o at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded.Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100 o is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.