A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

“…Furthermore, the logic synthesis feature of the digital PLL reduces the design time and has better programmability, portability, and testability when the PLL is converted to different CMOS process technologies. As a result, digital PLLs have recently gained broad interest as an alternative to conventional analog charge-pump based PLLs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15].…”

“…In recent years, the bang-bang digital PLL (BB-DPLL) has been widely researched as an attractive topology for a clock generator for SoC applications owing to its simple implementation and small area [9][10][11][12][13][14][15]. Figure 2 shows a top-level diagram of a conventional BB-DPLL.…”

“…Copyright ⓒ2016 SERSC Among several DCO topologies, a ring-based DCO circuit with a large unit gain is most commonly adopted to achieve a wide frequency-locking range, a small chip area, and a fast lock time for the clock generator [10][11][12][13][14]. However, when the high-order sigma-delta modulator is applied to a ring-based DCO with a large unit gain, its quantization noise becomes the dominant contributor to increase the jitter and PLL phase noise in the high-frequency offset region.…”

“…Figure 3 shows a second-order MASH sigma-delta modulator. Dithering streams of a high-order MASH sigma-delta modulator have been widely used not only to improve the effective frequency resolution but also to remove spurious tones of the DCO [1][2][3][4][5][6][7][8][9][10][11]. However, a wide dithering range of a high-order sigma-delta modulator increases the deterministic jitter; for instance, second and third-order sigma-delta modulators have maximal dithering gain ranges of 3×d I and 5×d I , respectively [14].…”

A latency-proof quantization noise reduction method for digitally-controlled ring oscillators

“…The first one in Fig. 2(a) is based on an inverter array with row and column digital inputs [1]- [2], and Fig. 2(b) shows the DAC based DCRO [3]- [4].…”