A modular current-mode classifier circuit for template matching application

Liu, Bin-Da; Chen, Chuen-Yau; Tsao, Ju-Ying

doi:10.1109/82.823544

Cited by 44 publications

(5 citation statements)

References 16 publications

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“…Distance calculation circuit (DCC) is responsible for the calculation of a distance between XðtÞ and W j ðtÞ vector in a given, jth, neuron. In the analog approach this block can be realized either as a voltage-mode [28,29] or a current-mode circuit [30][31][32]. Example circuits of this type have been reported in [32][33][34].…”

Section: Realization Of the Wta Nn In The Cmos Technologymentioning

confidence: 99%

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

Talaśka

Kolasa

Długosz

et al. 2015

Applied Mathematics and Computation

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Section: Realization Of the Wta Nn In The Cmos Technologymentioning

confidence: 99%

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

Talaśka

Kolasa

Długosz

et al. 2015

Applied Mathematics and Computation

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“…Further, the final addition operation after the multiplication step requires twice the number of bits of the input vector (as it is driven by multiplier outputs). Since this operation is performed iteratively over a large number of input vectors, alternative implementations involving analog current-mode designs of such computations are being actively explored [11,12,14]. The main advantage of this approach results from the fact that the addition/subtraction operation can be mapped to current flowing into/out of a circuit node (following Kirchhoff's current law).…”

Section: Proposed Approximate Distance Computing Unitmentioning

confidence: 99%

“…A digital comparator and subtractor unit computes the absolute difference between the two inputs. It is worth noting here that current-mode analog computing is also a popular mechanism to calculate the absolute difference between two inputs [11,12,14]. However, in that case, the inputs should be represented by analog voltages or currents, which require additional converting units to interface with external digital logic.…”

Section: Architecture Of the Proposed K-means Clustering Unitmentioning

confidence: 99%

“…However, despite the theoretical study and application of K-means clustering, efficient hardware implementation does not appear to have yet been achieved despite the simple and repetitive multiplication and addition operations required for distance calculation. Apart from the most intuitive approach to implementing clustering algorithms based on digital logic gates, various distance computing methods using analog [11][12][13][14][15] and mixed-mode design [16,17] have been proposed in the literature. As is well known, the digital-based approach can provide the most accurate and fast operating speed at the cost of area and power, while analog methods have comparable precision characteristics despite their simple structure.…”

Section: Introductionmentioning

confidence: 99%

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Energy Efficient Distance Computing: Application to K-Means Clustering

et al. 2022

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Distance computation between two input vectors is a widely used computing unit in several pattern recognition, signal processing and neuromorphic applications. However, the implementation of such a functionality in conventional CMOS design requires expensive hardware and involves significant power consumption. Even power-efficient current-mode analog designs have proved to be slower and vulnerable to variations. In this paper, we propose an approximate mixed-signal design for the distance computing core by noting the fact that a vast majority of the signal processing applications involving this operation are resilient to small approximations in the distance computation. The proposed mixed-signal design is able to interface with external digital CMOS logic and simultaneously exhibit fast operating speeds. Another important feature of the proposed design is that the computing core is able to compute two variants of the distance metric, namely the (i) Euclidean distance squared (L22 norm) and (ii) Manhattan distance (L1 norm). The performance of the proposed design was evaluated on a standard K-means clustering algorithm on the “Iris flower dataset”. The results indicate a throughput of 6 ns per classification and ∼2.3× lower energy consumption in comparison to a synthesized digital CMOS design in commercial 45 nm CMOS technology.

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“…In this paper we propose a new distance calculation circuit (DCC) that in the SOM is used to calculate distances between the input learning pattern X and weights vectors W of particular neurons. Most of DCCs proposed in the literature have been realized as analog circuits [5][6][7][8][9][10][11][12], working in either the voltage or the current mode. Such implementations require solving specific problems of an electronic nature.…”

Section: Introductionmentioning

confidence: 99%

Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

Długosz¹,

Kolasa²,

Talaśka³

et al. 2013

SSP

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This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm2.

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A modular current-mode classifier circuit for template matching application

Cited by 44 publications

References 16 publications

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology

Energy Efficient Distance Computing: Application to K-Means Clustering

Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

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