A modular router architecture desgin for Network on Chip

Abstract

Network on Chip is an efficient on-chip communication architecture for SoC architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC with multiple, connecting to other router and to a local IP core. This router architecture can be used later for building a NoC with standard or arbitrary topology with low latency and high speed and High maximal peak performance. The low latency and high speed is achieved by allowing for each input port a routing function which runs in parallel with Link controler and with distributed arbiters. To evaluate our approach, A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA thechnology, with different flit size.

Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques

“…The example topologies for NoC are mesh, 2D-torus etc. This architecture is based on an m x n mesh network where every router, except those at the edges, is connected to four neighboring routers and one computation resource (IP) through communication channel [9]. This topology allows integration of large number of IP cores in a regular shape structure.…”