A monadic approach to automated reasoning for Bluespec SystemVerilog

Richards, Dominic; Lester, David

doi:10.1007/s11334-011-0149-0

Cited by 7 publications

(4 citation statements)

References 47 publications

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“…Richards and Lester defined a shallow, monadic embedding of a subset of Bluespec into PVS and performed demonstrative proofs using the PVS theorem prover on a 50-line Bluespec design [55]. Their techniques may be complementary to our model checking approach for proving properties that are amenable to theorem proving.…”

Section: High-assurance Hardware Developmentmentioning

confidence: 99%

Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware

LeMay

Gunter²

2015

Lecture Notes in Computer Science

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Mobile devices are in roles where the integrity and confidentiality of their apps and data are of paramount importance. They usually contain a System-onChip (SoC), which integrates microprocessors and peripheral Intellectual Property (IP) connected by a Network-on-Chip (NoC). Malicious IP or software could compromise critical data. Some types of attacks can be blocked by controlling data transfers on the NoC using Memory Management Units (MMUs) and other access control mechanisms. However, commodity processors do not provide strong assurances regarding the correctness of such mechanisms, and it is challenging to verify that all access control mechanisms in the system are correctly configured. We propose a NoC Firewall (NoCF) that provides a single locus of control and is amenable to formal analysis. We demonstrate an initial analysis of its ability to resist malformed NoC commands, which we believe is the first effort to detect vulnerabilities that arise from NoC protocol violations perpetrated by erroneous or malicious IP.

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Section: High-assurance Hardware Developmentmentioning

confidence: 99%

Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware

LeMay

Gunter²

2015

Lecture Notes in Computer Science

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“…Moreover, more complex scheduling can be implemented using a few program combinators [15]: we look forward to implementing these in Fe-Si. [23] developed a shallow-embedding of a subset of Bluespec in PVS. While they do not address circuit generators nor the generation of RTL code, they proved the correctness of a three-input fair arbiter and a two-process implementation of Peterson's algorithm that complements our case studies (we have not attempted to translate these examples into Fe-Si).…”

Section: Comparison With Related Workmentioning

confidence: 99%

Formal Verification of Hardware Synthesis

Braibant

Chlipala²

2013

Computer Aided Verification

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We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.

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“…al. [18] proposed a more complete translation of Bluespec to PVS leveraging a monadic representation. Both of these focused on the task of getting the Bluespec design translated for the model checker faithfully.…”

Section: Related Workmentioning

confidence: 99%

Verification of microarchitectural refinements in rule-based systems

Dave

Katelman

King

et al. 2011

Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)

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Abstract-Microarchitectural refinements are often required to meet performance, area, or timing constraints when designing complex digital systems. While refinements are often straightforward to implement, it is difficult to formally specify the conditions of correctness for those which change cycle-level timing. As a result, in the later stages of design only those changes are considered that do not affect timing and whose verification can be automated using tools for checking FSM equivalence. This excludes an essential class of microarchitectural changes, such as the insertion of a register in a long combinational path to meet timing. A design methodology based on guarded atomic actions, or rules, offers an opportunity to raise the notion of correctness to a more abstract level. In rule-based systems, many useful refinements can be expressed simply by breaking a single rule into smaller rules which execute the original operation in multiple steps. Since the smaller rule executions can be interleaved with other rules, the verification task is to determine that no new behaviors have been introduced. We formalize this notion of correctness and present a tool based on SMT solvers that can automatically prove that a refinement is correct, or provide concrete information as to why it is not correct. With this tool, a larger class of refinements at all stages of the design process can be verified easily. We demonstrate the use of our tool in proving the correctness of the refinement of a processor pipeline from four stages to five.

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A monadic approach to automated reasoning for Bluespec SystemVerilog

Cited by 7 publications

References 47 publications

Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware

Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware

Formal Verification of Hardware Synthesis

Verification of microarchitectural refinements in rule-based systems

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