2007
DOI: 10.1016/j.sysarc.2007.01.010
|View full text |Cite
|
Sign up to set email alerts
|

A multi-channel architecture for high-performance NAND flash-based storage system

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
60
0

Year Published

2008
2008
2017
2017

Publication Types

Select...
6
3
1

Relationship

3
7

Authors

Journals

citations
Cited by 126 publications
(60 citation statements)
references
References 5 publications
0
60
0
Order By: Relevance
“…These issues include data placement, parallelism, write ordering, and workload management. A high performance and NAND flash memory based storage system is proposed in [Kang et al 2007]. The system consists of multiple independent channels, where each channel has multiple NAND flash memory chips.…”
Section: Fig 3 Ssd Logic Componentsmentioning
confidence: 99%
“…These issues include data placement, parallelism, write ordering, and workload management. A high performance and NAND flash memory based storage system is proposed in [Kang et al 2007]. The system consists of multiple independent channels, where each channel has multiple NAND flash memory chips.…”
Section: Fig 3 Ssd Logic Componentsmentioning
confidence: 99%
“…The total time required to retrieve data a is 0.088 ms and data b is retrieved directly after retrieving data a. Data accessing (retrieving and storing) in flash memory is carried out in three phases, 1) Setup, 2) Busy, and 3) Data transfer [24]. The accessing command is initialized in the setup phase.…”
Section: Flash Memory Characteristicsmentioning
confidence: 99%
“…As the demand for larger capacity and higher performance is growing, SSDs have usually adopted a multi-chip architecture [8]. According to the bus configuration, the architecture are broadly classified into two categories: shared control and shared bus architectures [9].…”
Section: Multi-chip Architecturementioning
confidence: 99%