A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Shin, Kyung-Wook; Kim, Hae-Ju

doi:10.5573/jsts.2012.12.1.24

Cited by 16 publications

(10 citation statements)

References 13 publications

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“…Indeed, FPGA implementations are often proposed [Peyic et al 2012;Marchand et al 2011;Shin and Kim 2012;Murugappa et al 2012] to prototype LDPC decoders and thus estimate the impacts of design decisions on BER performance. These FPGA prototypes are efficient in terms of throughput and hardware complexity.…”

Section: Positioning Of the Proposed Gpu-like Architecture In The Arcmentioning

confidence: 99%

GPU-like on-chip system for decoding LDPC codes

Gal

Jégo

2014

ACM Trans. Embed. Comput. Syst.

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Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based on abstract models of the system with real-time experiments under real-world conditions. GPU-like architecture is a promising approach to fully exploit the potential of FPGA-based acceleration platforms. In this article, an application-specific GPU-like architecture and a complete compilation framework for decoding LDPC codes are proposed. The interest in an applicationspecific GPU in comparison with current GPUs is detailed. Finally, real-time experimentations demonstrate the potential of the GPU-like decoder to investigate both algorithmic and architectural issues.

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Section: Positioning Of the Proposed Gpu-like Architecture In The Arcmentioning

confidence: 99%

GPU-like on-chip system for decoding LDPC codes

Gal

Jégo

2014

ACM Trans. Embed. Comput. Syst.

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“…Each 0 in the base matrix is expanded to a pxp zero sub matrix 0 and each 1 at position (u ,v) is expanded to p x p sub matrix T 1I . V that is obtained by right cyclic shifting a p x p identity matrix by k 1I , V columns [6]. [3].…”

Section: Qc-ldpc Code Constructionmentioning

confidence: 99%

Comparative analysis of single mode and multimode QC-LDPC decoder using modified belief propagation algorithm

Mankar¹,

Asutkar²,

Dakhole³

2015

2015 International Conference on Industrial Instrumentation and Control (ICIC)

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Low density parity check codes (LDPC) are appearing in an increasing number of applications which shows a performance close to the Shannon limit. The near Shannon limit error correction capability has lead LDPC codes to become the coding technique of choice in many communications and storage systems since their introduction. LDPC have good error correcting performance which enables efficient and reliable communication. Quasi-cyclic LDPC codes known as a subclass of LDPC codes are used whose parity check matrices consists of circulant permutation matrices. This character of QC-LDPC codes opens the door for the multi-mode. In the present work partially parallel architecture for single mode and multi-mode quasi-cyclic low density parity check (QC-LDPC) decoders have been designed using modified belief propagation algorithm. QCLDPC codes require less memory as compared to LDPC codes and resource occupied by the single mode decoder is only a little more than the multi-mode decoder. This decoder is modeled using Verilog software, synthesized and performed place and route for the design using Xilinx ISE 13.2.

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“…Although the algorithms and approximation techniques are quite similar, the proposed architectures show much variety in each implementation. ASIC implementations [3,4,5,6,7,8,9] mainly focus on squeezing highly parallelized decoders into smaller silicon areas, whereas FPGA implementations [10,11,12,13,14,15,16,17] focus on efficient utilization of the inherent resources. Therefore, the challenge of optimizing large permutation networks in ASIC designs has mostly turned into designing dynamic RAM-based networks in FPGA designs.…”

Section: Introductionmentioning

confidence: 99%

Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

Yesil

Arslan

2014

2014 12th International Conference on Signal Processing (ICSP)

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This paper presents a generic RAM based FPGA architecture for decoding of Multi Rate Quasi-Cycling LDPC codes. RAM based decoding enables us to reduce permutation networks into simple address controllers. Moreover, utilizing Block RAMs with various aspect ratios in an FPGA provides flexibility ranging from area driven compact designs to fully parallelized high throughput designs. Utilizing the read-first property of the RAMs, the proposed design efficiently exploits the dual port Block RAM resources by accessing all the four ports at the same time. Such facilities of recent FPGA devices have been combined with the well known layered decoding algorithm with non-linearly mapped Min-Sum approximation in order to obtain area efficient yet high throughput decoders. The proposed decoder architecture has been verified on Xilinx XC7Z020 FPGA device for IEEE 802.16e Wimax LDPC codes. 340Mbps of information throughput has been observed at an operating frequency of 150MHz.

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A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Cited by 16 publications

References 13 publications

GPU-like on-chip system for decoding LDPC codes

GPU-like on-chip system for decoding LDPC codes

Comparative analysis of single mode and multimode QC-LDPC decoder using modified belief propagation algorithm

Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

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