A multi-objective floorplanner for shuttle mask optimization

Xu, Gang; Tian, Ruiqi; Pan, David Z.; Wong, Martin D. F.

doi:10.1117/12.569345

Cited by 25 publications

(24 citation statements)

References 16 publications

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“…As in [14], two dies D and D on a reticle are said to be in "dicing conflict" if they are either in horizontal dicing conflict or vertical dicing conflict. The "conflict graph" R c = (D, E c ) is the graph with vertices corresponding to the dies and edges connecting pairs of dies in dicing conflict.…”

Section: A Integer Linear Program For Restricted Mdpsmentioning

confidence: 99%

“…Xu et al [14] assume that each wafer uses exactly one horizontal dicing plan and one vertical dicing plan for all projection rows/columns within a wafer. This assumption allows them to use a coloring-based heuristic that gives good results for test cases with a large volume requirement.…”

Section: A Integer Linear Program For Restricted Mdpsmentioning

confidence: 99%

“…2) Single-row and -column dicing plan (SRCDP)-assumption-based floorplanners employ the assumption that all rows and columns of reticle images within a wafer are diced using the same set of cuts. Xu et al [14], [15] formulate the dicing problem as a minimum coloring problem. Wu and Lin [11] extend the minimumcoloring-based dicing approach by proposing three ILP formulations for optimal minimum coloring.…”

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confidence: 99%

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Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction

Chiang

Kahng²,

Sinha³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The aggressive scaling of very large-scale integration feature size and the pervasive use of advanced reticle enhancement technologies lead to dramatic increases in mask costs, pushing prototype and low-volume production designs to the limit of economic feasibility. Multiproject wafers (MPWs), or "shuttle" runs, provide an attractive solution for such designs by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce complexities that are not encountered in typical single-project wafers. Recent works on wafer dicing adopt one or more of the following assumptions to reduce problem complexity: 1) equal production volume requirement for all designs; 2) same dicing plan used for all wafers or for all rows/columns of reticle images on a wafer; 3) unrealistic wafer models such as a rectangular array of projections; and 4) fixed wafer shot-map. Although using one or more of the aforementioned assumptions makes the problem solvable, the performance of the solutions is degraded. In this paper, a comprehensive MPW flow aimed at minimizing the number of wafers needed to fulfill given die production volumes is proposed. The proposed flow includes two main steps: 1) multiproject reticle floorplanning and 2) wafer shot-map and dicing plan definition. For each of these steps, improved algorithms are proposed as follows. The proposed reticle floorplanner uses a hierarchical quadrisection combined with simulated annealing to generate "diceable" floorplans, observing given maximum reticle sizes. The proposed dicing planner allows multiple side-to-side dicing plans for different wafers and different reticle projection rows/columns within a wafer and further improves the dicing yield by partitioning each wafer into a small number of parts before individual die extraction. A wafer shot-map definition heuristic is also proposed in order to fully utilize round wafer real estate by extracting the maximum number of functional dies from both fully and partially printed reticle images. Experiments on industry test cases show that the proposed methods outperform significantly not only previous methods in the literature but also reticle floorplans manually designed by experienced engineers.

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Section: A Integer Linear Program For Restricted Mdpsmentioning

confidence: 99%

Section: A Integer Linear Program For Restricted Mdpsmentioning

confidence: 99%

mentioning

confidence: 99%

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Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction

Chiang

Kahng²,

Sinha³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, some of the previous works [1,2] did not consider the side-to-side dicing technology. Some of them [1,2,3,4,5] did not aim at maximizing the wafer utilization but aim at minimizing reticle area. Kahng [6] revisited the MPW problem and tried to minimize the number of wafers used.…”

Section: Figure 1: a Multi-project Wafermentioning

confidence: 99%

Shuttle mask floorplanning with modified alpha-restricted grid

Ching

Young

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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“…Xu et al (2003) employ slicing trees to perform reticle area minimization while taking die-to-die inspection into consideration. Xu et al (2004; further consider metal density optimization (Tian et al, 2001) to improve wafer planarization. These methods consider only reticle area minimization.…”

Section: Related Work For Rfpmentioning

confidence: 99%