A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage

Ali, Tarek; Olivo, Ricardo; Lederer, Maximilian; Hoffmann, R.; Steinke, P.; Zimmermann, Katrin; Mühle, Uwe; Seidel, Konrad; Müller, Johannes; Polakowski, P.; Kühnel, Kati; Czernohorsky, M.; Kämpfe, Thomas; Rudolph, Matthias; Pätzold, B.; Lehninger, David; Müller, F.

doi:10.1109/iedm19573.2019.8993642

Cited by 105 publications

(50 citation statements)

References 3 publications

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“…This property can be attributed to its superior endurance and write speed as compared to Flash, significantly higher on-to-off current ratio than MRAM, as well as the negligible impact from random telegraphic noise due to charge-based operation, unlike RRAM. The advantage of HZO over other perovskite ferroelectric materials and Sidoped hafnium oxides (HSO) has been mentioned in previous reports, which involves ease of deposition by the ALD process, scalability to thin film, and lower process temperature (Muller et al, 2012;Jerry et al, 2017;Kim H. et al, 2018;Ali et al, 2019;Ni et al, 2019;Cheema et al, 2020). Recent reports have also shown that low process temperature, superior interface quality, and reducing the numbers of defect sites in HZO improve the endurance of the HZO-based transistors (Dutta et al, 2020;De et al, 2021a;De et al, 2021b;Khakimov et al, 2021).…”

Section: Introductionmentioning

confidence: 99%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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This work presents 2-bits/cell operation in deeply scaled ferroelectric finFETs (Fe-finFET) with a 1 µs write pulse of maximum ±5 V amplitude and WRITE endurance above 109 cycles. Fe-finFET devices with single and multiple fins have been fabricated on an SOI wafer using a gate first process, with gate lengths down to 70 nm and fin width 20 nm. Extrapolated retention above 10 years also ensures stable inference operation for 10 years without any need for re-training. Statistical modeling of device-to-device and cycle-to-cycle variation is performed based on measured data and applied to neural network simulations using the CIMulator software platform. Stochastic device-to-device variation is mainly compensated during online training and has virtually no impact on training accuracy. On the other hand, stochastic cycle-to-cycle threshold voltage variation up to 400 mV can be tolerated for MNIST handwritten digits recognition. A substantial inference accuracy drop with systematic retention degradation was observed in analog neural networks. However, quaternary neural networks (QNNs) and binary neural networks (BNNs) with Fe-finFETs as synaptic devices demonstrated excellent immunity toward the cumulative impact of stochastic and systematic variations.

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Section: Introductionmentioning

confidence: 99%

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Baig

Qiu

et al. 2022

Front. Nanotechnol.

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“…Note that device variability may present for the highly scaled FeFET due to a smaller number of ferroelectric domains. It can be addressed by reducing the grain size via decreasing the ALD deposition temperature [16], increasing annealing temperature [17] and inserting Al 2 O 3 in HZO film [18]. To further unveil the polarization switching characteristics of the FeFETs, different pulse width was utilized and the results are shown in Fig.…”

Section: Results and Discussion A Memory Window For N-and P-fefetsmentioning

confidence: 99%

Reduced Asymmetric Memory Window Between Si-Based n- and p-FeFETs With Scaled Ferroelectric HfZrOₓ and AlON Interfacial Layer

Peng

Kao

et al. 2021

IEEE Electron Device Lett.

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The Si-based n-and p-FeFET with 5-nm ferroelectric (FE) HfZrO x (HZO) and high-k AlON interfacial layer (IL) were fabricated for the comparison of memory characteristics and reliability. The memory window (MW) of 1.37 V and 1.25 V are obtained by the n-and p-FeFET respectively by applying pulses of ±3.8 V/50 µ s. The typical MW asymmetry for both types of FeFETs is significantly reduced which is attributed to the reduced remanent polarization (P r ) from the highly scaled HZO and the enhanced voltage drop across the HZO as well as the improved interfacial quality from the AlON IL. In addition, the p-FeFET demonstrates a MW of 1.02 V up to 10 5 cycles with a long pulse 10 −4 s, superior to that of the n-FeFET due to the mitigated hot-electrons induced hole generation. Furthermore, the p-FeFET shows comparable retention performance with the n-FeFET. These results indicate that the p-FeFET possesses the competence of future memory applications without adding process complexity and introducing new substrate material. Index Terms-Non-volatile memory, ferroelectric HfZrO x , p-FeFET, pulsed I D -V G , memory window, reliability. I. INTRODUCTION S INCE ferroelectricity has been observed in doped-HfO 2 [1], it is regarded as one of the promising materials to implement ferroelectric field-effect transistors (FeFETs) for the applications of memory and neuromorphic computing due to its high compatibility with the incumbent VLSI technology. Although HfO 2 -based FeFETs have demonstrated several competitive advantages including scalability, low operation voltage, fast switching speed [2], robust endurance [3], and non-destructive readout ability [4], most of prior works focused on the investigation of n-channel FeFETs (n-FeFETs), only few researches for p-channel FeFETs (p-FeFETs) were studied [5]-[9]. To maximize the flexibility of circuit design in novel CMOS technology and enable full ferroelectric hierarchy [5], the characteristics of p-FeFETs should be also

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“…In this paper, the merits of the ferroelectric film lamination using an alumina interlayer are presented in relation to one transistor (1T) FeFET concept. This concept was recently reported in [17]. This paper aims to provide detailed insights into and an understanding of this novel device concept.…”

Section: Introductionmentioning

confidence: 97%

Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

Ali

Kühnel

Olivo

et al. 2021

Electronic Materials

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A multi-level cell (MLC) operation as a 1–3 bit/cell of the FeFET emerging memory is reported by utilizing optimized Si doped hafnium oxide (HSO) and hafnium zirconium oxide (HZO) based on ferroelectric laminates. An alumina interlayer was used to achieve the thickness independent of the HSO and HZO-based stack with optimal ferroelectric properties. Various split thicknesses of the HSO and HZO were explored with lamination to increase the FeFET maximum memory window (MW) for a practical MLC operation. A higher MW occurred as the ferroelectric stack thickness increased with lamination. The maximum MW (3.5 V) was obtained for the HZO-based laminate; the FeFETs demonstrated a switching speed (300 ns), 10 years MLC retention, and 104 MLC endurance. The transition from instant switching to increased MLC levels was realized by ferroelectric lamination. This indicated an increased film granularity and a reduced variability through the interruption of ferroelectric columnar grains. The 2–3 bit/cell MLC levels and maximum MW were studied in terms of the size-dependent variability to indicate the impact of the ferroelectric area scaling. The impact of an alumina interlayer on the ferroelectric phase is outlined for HSO in comparison to the HZO material. For the same ferroelectric stack thickness with lamination, a lower maximum MW, and a pronounced wakeup effect was observed in HSO laminate compared to the HZO laminate. Both wakeup effect and charge trapping were studied in the context of an MLC operation. The merits of ferroelectric stack lamination are considered for an optimal FeFET-based synaptic device operation. The impact of the pulsing scheme was studied to modulate the FeFET current to mimic the synaptic weight update in long-term synaptic potentiation/depression.

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A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage

Cited by 105 publications

References 3 publications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Reduced Asymmetric Memory Window Between Si-Based n- and p-FeFETs With Scaled Ferroelectric HfZrOₓ and AlON Interfacial Layer

Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

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