A mutual characterization based SAR ADC self-testing technique

Lin, Hsiu-Ting; Huang, Xiaolin; Huang, Jiun-Lang

doi:10.1109/ets.2013.6569365

Cited by 6 publications

(6 citation statements)

References 15 publications

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“…The approach in [9] deals with a differential split-capacitor SAR ADC (SC-SAR ADC) topology. One branch of the differential SC-SAR ADC measures the other, and similarly in [10] for a single-ended case, one of the sub-DACs extracts the bit-weights of the adjacent sub-DAC. The advantage of not needing extra analog circuitry is traded with higher test times, since multiple iterations are needed to converge to an accurate measurement.…”

Section: Previous Workmentioning

confidence: 99%

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

Feitoza¹,

Barragán²,

Mir³

2019

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

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This work presents reduced-code strategies for the static linearity test of successive-approximation analog-to-digital converters. Reduced-code techniques for ADC static linearity test may drastically reduce the test time for static linearity characterization. These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the implementation of these techniques for three widely used SAR ADC topologies. Namely, we consider SAR ADCs based on binary-weighted capacitive DACs, split-capacitor DACs and segmented DACs. The proposed techniques are validated by behavioral simulations on three SAR ADC case studies.

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Section: Previous Workmentioning

confidence: 99%

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

Feitoza¹,

Barragán²,

Mir³

2019

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

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“…Obviously, the method can only be applied to the differential type and the bits in LSB side are not corrected. In [10,11] two similar calibration methods are presented. One sub-array is utilized to test the other one in the same branch without additional analog circuits.…”

Section: Introductionmentioning

confidence: 97%

“…One sub-array is utilized to test the other one in the same branch without additional analog circuits. But the calibration techniques in [9][10][11] still have some drawbacks. First, they are foreground calibration and need an extra calibration operation phase; second, the mismatch correction of any capacitor is dependent on the results of the correction of all the previous capacitors.…”

Section: Introductionmentioning

confidence: 98%

A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture

Cao

Zhu

et al. 2015

Microelectronics Journal

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“…It is also common that complex mixed-signal SOCs include more than one ADC and DAC. These data converters require anti-aliasing filters and reconstruction filters to remove aliasing noise [4] Digitally assisted analog design [5][6] and integrated transceiver calibration [7][8] approaches are gaining popularity in ensuring efficient and reliable mixed-signal systems in nano-scale CMOS technologies. One design aspect is to equip analog blocks with performance-tuning features that allow the recovery from process variations and faults.…”

Section: Introductionmentioning

confidence: 99%

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

Jung¹,

Kim²,

Kim³

2020

JICS

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This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

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A mutual characterization based SAR ADC self-testing technique

Cited by 6 publications

References 15 publications

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs

A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

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