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An automatic test pattern generation (ATPG) technique, which simultaneously reduces capture and shift power during scan testing, is presented. This ATPG performs power reduction during dynamic test compaction so the test length overhead is very small. This low-power test generator implements several novel techniques, such as parity backtrace, confined propagation, dynamic controllability and post-fill test regeneration. The experimental data on ISCAS benchmark circuits show that the peak capture power and the peak shift power are reduced by 31% and 26%, respectively.Past research in low-power test generation can be summarised as follows. Wang and Gupta [8] add novel testability measure to traditional test generation algorithm and effectively reduce the average power. Genetic algorithm was proposed to remove redundant test sequences without fault coverage degradation [9], which is effective for functional (fully sequential)

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