A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$  Error Detection and Correction Technique

Kim, Seong-Jong; Cerqueira, Joao P.; Seok, Mingoo

doi:10.1109/tvlsi.2019.2910792

Cited by 15 publications

(14 citation statements)

References 31 publications

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“…To avoid this hassle, many near-threshold EDaC designs opt for a latch based pipeline [10], [12], [15]. This circumvents the need for hold-constraints that match the DW and allows to use halve the clock period as a DW.…”

Section: B Detection Windowmentioning

confidence: 99%

“…However, a latch based pipeline exhibits a significant area and energy overhead compared to a FF pipeline [10], [12], [14]. Furthermore, the works in [12] & [15] combine this with a sparse insertion-rate where the DW is shared over multiple pipeline stages through time-borrowing. Despite the fact that a complex static-timing analysis is done to guarantee that the total borrowing never exceeds the DW, this makes it easier for critical signals to be masked from the detectors by the processor's activity pattern.…”

Section: B Detection Windowmentioning

confidence: 99%

“…In a typical processor architecture, this can be achieved through instruction replay [8] or bubble insertion [10]. Yet, for non-processor architectures such as neural networks it is not always possible to efficiently implement this approach [15]. Finally, in (3), the late-arriving data is bypassed towards the next pipeline stage.…”

Section: Error Correctionmentioning

confidence: 99%

“…Yet, as [13] shows, it is also possible to implement this approach using so called soft-edge FFs that forward data in the event of a timing error. However, to avoid the risk of timing error cascades that fall beyond the detection and/or correction capabilities of the system, masking approaches have to impose a maximum borrowing limit [16] or increase the slack of the stage where the borrowing takes place [12], [15], [20].…”

Section: Error Correctionmentioning

confidence: 99%

See 3 more Smart Citations

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Uytterhoeven

Dehaene

2022

IEEE J. Solid-State Circuits

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This paper presents a timing error detection and correction (EDaC) technique optimized for near/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional holdconstraints on monitored paths by instantaneously checking for late activity. Further, two correction methods are discussed, a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8 % and 2.1 % area overhead for the detection and correction respectively. Silicon measurements validate the EDaC system from 0.25 V to 0.7 V (1 MHz to 200 MHz) and show that it recovers all voltage margins in the near/sub-threshold region. The design achieves a MEP of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48 % to 17.6 % with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12 % energy overhead compared to its ideal non-margined critical operation point.

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Section: B Detection Windowmentioning

confidence: 99%

Section: B Detection Windowmentioning

confidence: 99%

Section: Error Correctionmentioning

confidence: 99%

Section: Error Correctionmentioning

confidence: 99%

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Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Uytterhoeven

Dehaene

2022

IEEE J. Solid-State Circuits

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“…Lowering supply voltages to the near-threshold voltage (NTV) region is one of the effective techniques for achieving higher energy efficiency in energy-constrained circuits [1][2][3]. However, NTV operations also cause new challenges due to the increasing delay caused by process, voltage and temperature (PVT) variations under the scaling voltages [2].…”

Section: Introductionmentioning

confidence: 99%

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

Fan

Líu

et al. 2022

Electronics

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Near-threshold voltage (NTV) operation has the potential to improve the energy efficiency of digital integrated circuits. However, the use of a conservative timing guard band to avoid the timing errors introduces excessive timing margins, thus causing larger energy dissipation in the NTV region. An error-tolerant design based on timing error detection and correction circuits has been shown to be a promising solution to mitigate these issues. This paper presents a light-weight timing error-tolerant flip-flop (ETFF) design. This design detects timing errors using a node transition signal detector with only nine transistors and corrects these errors during the same clock cycle. Moreover, transistor sizing is explored to optimize the trade-off between performance and area overhead. The proposed ETFFs are inserted into a monitored circuit by replacing original flip-flops at timing-monitored points. To further reduce the overhead, we develop a mean-time-to-failure-aware method to select the monitored points by simultaneously considering the critical path coverage and activation rates of flip-flops. The simulation results show that a CNN accelerator using the proposed timing error-tolerant design implemented in the SMIC CMOS 40 nm process can robustly work at 1.1–0.3 V with only 3.5% area overhead. Furthermore, this design reduces the area overhead by 54.68% and improves the energy efficiency by 53.69% at 0.6 V, compared with the Razor flip-flop design. The advantage of the proposed design lies in that it requires smaller circuit overheads and can work reliably in a wider range of supply voltages.

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Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

Sreekumar,

Shankar,

Reddy

2025

Integration

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A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction Technique

Cited by 15 publications

References 31 publications

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

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