A new analytical model for determination of breakdown voltage of Resurf structures

Križaj, Dejan; Charitat, G.; Amon, S.

doi:10.1016/0038-1101(96)00051-2

Cited by 20 publications

(7 citation statements)

References 3 publications

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“…In order to achieve a geometry parameters can lead to a movement of breakdown better agreement between analytical and numerical results, location among the P+N junction, the N+N junction and the the ionization constant A is adjusted with the new value of upper-surface of the buried oxide layer. As a result, the 1-1.5 *10-35V-7cm6 [8]. As illustrated in Fig.…”

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confidence: 86%

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A new two dimensional analytical breakdown model of SOI RESURF devices

Guo

Zhang

2007

2007 International Conference on Communications, Circuits and Systems

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In this paper, a new breakdown model of SOI electrostatic potentials and electric fields for both the RESURF devices is proposed based on solving 2-D Poisson completely and incompletely depleted drift region. The equation. The approach explores the physical insights of the availability of the model is verified by the fair agreement lateral and vertical breakdowns for both of the completely and between the analytical results and numerical simulations. At incompletely depleted drift regions. Analytical 2-D electrostatic last, as an application of the model, 220V LDMOSFET is potential and electric fields distributions are compared with designed and fabricated on a SOI wafer with a 3gm-thick top the simulating results by MEDICI, The impacts of the Si layer and a 1.5gm-thick buried oxide layer. geometry parameters on the breakdown voltage are also investigated by the analytical model and numerical simulation. A well agreement between the analytical and simulating results II. ANALAYTICAL MODEL proofs the availability of the model. Finally, as a further A schematic cross section of a basic SOI RESUR-F device experimental verification, LDMOS with a breakdown voltage is illustrated in Fig. 1. Such a device can be considered as a of 220V was fabricated on a bonding SOI wafer with a top composite of a lateral P+N diode and a vertical SIS (Siliconsilicon thickness of 3.O1m and a buried oxide thickness of Insulate-Silicon) structure. Under the reverse-biased applied 1.5*m. voltage V a lateral space charge depletion region extends aprf rom the P N junction to the N+N junction, while a vertical

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confidence: 86%

“…(17) into (4), so A,2 (X,y) =(al2ex +b,2ex)(c,2 cosAy+d12 sin2y). (8) (18) But the following form is also a solution. L !…”

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confidence: 96%

A new two dimensional analytical breakdown model of SOI RESURF devices

Guo

Zhang

2007

2007 International Conference on Communications, Circuits and Systems

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“…Silicon is an established semiconductor material for high voltage power devices, such as for example super-junction structures and lateral RESURF structures (REduced SURface Field). These devices are based on a charge compensation effect between p-and n-doped regions [1][2][3][4]. Especially, lateral power devices form an important part of high voltage integrated circuits for CMOS devices.…”

Section: Introductionmentioning

confidence: 99%

“…For reliability reasons, a reduced electric field at the surface of SiC-devices is much more important than in Si-devices, due to the higher electric field. However, optimal parameters for the implantation depth and doping concentration are essential for the achievement of a reduced surface field [1][2][3][4], which is described in the following.…”

Section: Introductionmentioning

confidence: 99%

Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

Weisse

Mitlehner

Frey

et al. 2019

MSF

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In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

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“…The theory of these superjunctions is well described in [31]. The idea behind this RESURF or superjunction concept is to have a relatively highly doped drift region (Low R ON ) while maintaining the high BV s [32] associated with a constant electric field distribution along the current flow direction.…”

Section: The Resurf Principlementioning

confidence: 99%

Field-plate assisted RESURF power devices : gradient based optimalization, degradation and analysis

Boksteen¹

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A new analytical model for determination of breakdown voltage of Resurf structures

Cited by 20 publications

References 3 publications

A new two dimensional analytical breakdown model of SOI RESURF devices

A new two dimensional analytical breakdown model of SOI RESURF devices

Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

Field-plate assisted RESURF power devices : gradient based optimalization, degradation and analysis

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