A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications

Mukherjee, Adrija; Debnath, Papiya; Nirmal, D.; Chanda, Manash

doi:10.1016/j.mejo.2023.105689

Cited by 6 publications

(1 citation statement)

References 13 publications

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“…Therefore, the proposed device can be preferred over Junction-less Double Gate MOSFET for high-speed [37][38][39][40] and lowpower consumption applications in the subthreshold regime as a possible candidate to replace conventional CMOS devices 11 (c). From 11 (d), it is obvious that in the sub-threshold regime, significant logic swing [41][42] can be obtained which also proves the efficacy of the device in the sub-threshold regime [43][44][45][46][47][48].…”

Section: Cmos Inverter Based On the Proposed Devicementioning

confidence: 74%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

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In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

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