A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's

Abstract

A continuous-time offset cancelation and gain calibration strategy is proposed for open-loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide-bits digital processor for offset and gain-error correction.Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input-referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Postlayout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14-bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB.

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

“…[1][2][3] Among various ADCs' architectures like pipelined ADCs, deltasigma ADCs, and single-slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency. [4][5][6][7] Furthermore, as the feature size of CMOS devices are scaling down, the conversion rate of SAR ADCs improves. Hence, the SAR ADCs are the most attractive architecture for deep submicron CMOS technologies.…”

“…The demand for high‐speed and low‐power ADCs for battery‐operated systems like medical imaging, CMOS image sensors, mobile, and wearable devices are increased substantially in recent years 1–3 . Among various ADCs' architectures like pipelined ADCs, delta‐sigma ADCs, and single‐slope ADCs, the successive approximation register (SAR) ADCs are spotted for excellent power efficiency 4–7 . Furthermore, as the feature size of CMOS devices are scaling down, the conversion rate of SAR ADCs improves.…”