A new calibration method for current steering DACs

Abstract

A new calibration method for current steering DACs (digital to analog converters), whose main idea is to add compensation currents of the same value to the most sensitive current sources, is proposed. Some DC Monte-Carlo analyses are used to choose the optimal value for the correction current. The choice of the most sensitive current sources as well as the finding of the optimal combination of the corrected sources are done by steady state simulations and measurements. The SFDR (spurious free dynamic range) of a 8 bits DAC is improved with 5.5 dB using this method.

Design of a 8 bit current-steering DAC for a GSM transmitter

“…In [2] a segmented 5+3 architecture of the current steering DAC (Fig. 3) is used in order to reduce glitches because the switching current is smaller (binary DAC) and to use the layout area effectively (unary DAC).…”

“…Moreover, the synchronous control of the differential pair is performed by a latch, which is updated on the positive edge of the clock signal. The use of a latch is necessary because of the binary to thermometric decoder which can delay the data signal significantly [2]. Furthermore, using biasing current transfer will minimize the effect of layout parasitic elements.…”

“…Using this calibration method a minimal total harmonic distortion at the output of the DAC is targeted. The calibration method used for the DAC is described in [2].…”

“…In previous works [2,3] a segmented 5+3 architecture of the current steering DAC has been discussed, the main blocks being designed using a generic design kit of a 90μm technology provided by CADENCE. A new calibration method with using two algorithms for correction current value has been proposed [2,3].…”

“…A new calibration method with using two algorithms for correction current value has been proposed [2,3].…”