A new complementary hetero-junction vertical Tunnel-FET integration scheme

Rooyackers, R.; Vandooren, A.; Verhulst, Anne S.; Walke, A.; Devriendt, K.; Locorotondo, S.; Demand, M.; Bryce, George; Loo, Roger; Hikavyy, Andriy; Vandeweyer, T.; Huyghebaert, Cedric; Collaert, N.; Thean, Aaron

doi:10.1109/iedm.2013.6724558

Cited by 57 publications

(35 citation statements)

References 11 publications

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“…Later on, a further improvement of oncurrent of 180 µA/µm has been achieved by Zhou et al [8] in a GaSb-InAs TFET. Recent advancement in complementary TFET process [9,10] has further highlighted both the performance improvement and process compatibility for TFET technology.…”

Section: A Tunnel Fet Device Designmentioning

confidence: 99%

Enabling Power-Efficient Designs with III-V Tunnel FETs

Kim

Liu

Swaminathan

et al. 2014

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high g m /I DS , unidirectional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.Index Terms -Steep-slope devices, ultra-low power, lowvoltage, III-V Tunnel FET (TFET).

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Section: A Tunnel Fet Device Designmentioning

confidence: 99%

Enabling Power-Efficient Designs with III-V Tunnel FETs

Kim

Liu

Swaminathan

et al. 2014

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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“…To reduce the operation voltage, steeper subthreshold characteristic is one solution, which can be achieved by steep-slope device. Tunnel field-effect transistors (FETs) are candidate of steep-slope devices that have been reported to realize subthreshold slope (SS) of sub-60 mV/decade, which is smaller than the SS limitation for conventional metal-oxide-semiconduc tor FETs (MOSFETs) [1][2][3][4][5][6][7][8][9][10]. Since tunnel FETs (TFETs) are assumed to have ultralow voltage operation, the threshold voltage (V th ) control and design requirements for TFETs are severe compared with those for MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

Mizubayashi

Fukuda

Mori

et al. 2015

Solid-State Electronics

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“…Tunnel FETs (TFETs) are the most promising steep-slope devices for ultralow-voltage operation [1][2][3][4]. The BTI degradation of TFETs is their most important reliability issue [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Understanding of BTI for tunnel FETs

Mizubayashi

Mori

Fukuda

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

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We systematically investigated the NBTI degradation of Si-channel p-type tunnel FETs (pTFETs). The NBTI degradation mechanism of pTFETs is almost the same as that of pFETs. It was clarified that the NBTI degradation of pTFETs is only caused by the trap charge and the interface state degradation located in the tunneling region near the n + source/gate edge. Furthermore, in terms of the BTI degradation of n-and p-type TFETs, although the injection sources of carriers inducing PBTI and NBTI are different, applying a drain bias corresponding to the operation conditions has an effect on the BTI lifetime improvement of n-and p-type TFETs. IntroductionTunnel FETs (TFETs) are the most promising steep-slope devices for ultralow-voltage operation [1][2][3][4]. The BTI degradation of TFETs is their most important reliability issue [5][6][7]. The main differences between TFETs and FETs are the operation mechanism and the polarities of the source/drain. TFETs operate by band-to-band tunneling (BTBT) from the source to the channel, and the polarity of the source/drain for TFETs is asymmetric. In n-type TFETs (nTFETs), by a positive bias stress, the threshold voltage (V th ) shifts in the positive direction, while the average subthreshold slope (SS ave ) is not degraded [7]. We have reported that the PBTI lifetime of nTFETs is improved by applying a drain bias, because the PBTI degradation is mainly caused by electron injection from the n + drain [7]. However, the NBTI degradation of pTFETs has been hardly reported and has not been fully understood yet (Fig. 1). In this work, we investigated the NBTI degradation of pTFETs, to systematically understand the BTI of TFETs. For pTFETs, since the tunneling locally occurs near the n + source/gate edge, the impacts of the trap charge and the interface state degradation located in the tunneling or nontunneling region on NBTI were quantitatively examined by simulation. Finally, we investigated the impact of tunneling carriers on the NBTI degradation of pTFETs.

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A new complementary hetero-junction vertical Tunnel-FET integration scheme

Cited by 57 publications

References 11 publications

Enabling Power-Efficient Designs with III-V Tunnel FETs

Enabling Power-Efficient Designs with III-V Tunnel FETs

Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

Understanding of BTI for tunnel FETs

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