Enabling Power-Efficient Designs with III-V Tunnel FETs

Kim, Moon Seok; Liu, Huichu; Swaminathan, Karthik; Li, Xueqing; Datta, Suman; Narayanan, Vijaykrishnan

doi:10.1109/csics.2014.6978551

Cited by 13 publications

(3 citation statements)

References 30 publications

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“…In addition to the steep-slope switching characteristic, HTFET also exhibits some unique features shown in Fig. 2 [21]. The first feature is the unidirectional tunneling that makes TFET conducting current almost drain-to-source only in a moderate voltage range.…”

Section: Tfetmentioning

confidence: 99%

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures

George

et al. 2017

IFIP Advances in Information and Communication Technology

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In recent years, the concept of Internet-of-Things (IoT) has attracted significant interests. Required by the applications, the IoT power optimization has become the key concern, which relies on innovations from all levels of device, circuits, and architectures. Meanwhile, the energy efficiency of existing IoT implementations based on the CMOS technology is fundamentally limited by the device physics and also the circuits and systems built on it. This chapter focuses on a different dimension, exploring how emerging beyond-CMOS devices, such as tunnel field effect transistor (TFET) and negative capacitance FET (NCFET), and the circuits and architectures built upon them, could extend the low-power design space to enable IoT applications with beyond-CMOS features.

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Section: Tfetmentioning

confidence: 99%

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures

George

et al. 2017

IFIP Advances in Information and Communication Technology

Self Cite

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“…The current generation mechanism in TFETs is band to band tunneling of carriers across a reversed biased PN junction [1]. Nowadays, III-V TFETs with small and direct band gap have acceptable ON-current compared to those of MOSFETs [2]. Therefore, unlike MOSFETs, reducing the (leakage) power consumption is possible for TFETs without any degradation in the performance.…”

Section: Introductionmentioning

confidence: 99%

Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

Hemmat¹,

Kamal²,

Afzali-Kusha³

et al. 2017

IFIP Advances in Information and Communication Technology

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In this work, to improve the timing yield of Tunnel Field Effect Transistor (TFET) circuits in the presence of process variations as well as their softerror resiliency, we propose replacing some of TFET-based gates by MOSFETbased ones. The effectiveness of the proposed TFET-MOSFET hybrid implementation of the circuits are investigated by first studying the impacts of the process variation on the performances (I-V characteristics) of both homojunction InAs TFETs and MOSFETs. Next, to analyze the soft error rate of the circuits, the particle hit-induced transient current profiles of these devices are extracted. Based on these studies, a hybrid TFET-MOSFET circuit design approach which improves the reliability and soft-error resiliency compared to those of pure TFET-based circuits is suggested. Finally, the efficacy of the design approach is investigated by applying it to some circuits of ISCAS'89 benchmark package.

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“…The direct bandgap feature of these materials provided a higher ON current, improving the ratio for highperformance low-power circuits. Hence, they could be considered as a good candidate for realizing analog and digital circuits [5]. The performance and power/energy consumption of III-V TFETs have been investigated in several works (see, e.g., [1], [6], and [7]).…”

Section: Introductionmentioning

confidence: 99%

Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs

Hemmat

Kamal

Afzali-Kusha

et al. 2016

Solid-State Electronics

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In this paper, the impact of physical parameter variations on the electrical characteristics of III-V TFETs is investigated. The study is performed on the operations of two optimized ultra-thin 20nm double-gate transistors. The two device structures are InAs homojunction TFET and InAs-GaAs0.1Sb0.9 heterojunction TFET. The operation parameters are the ONcurrent, OFF-current, and threshold voltage. The investigation is performed at the device level, using a device simulator and the Monte-Carlo simulation approach is exploited to extract the distribution of electrical parameters in the presence of the process variation. The results reveal that the operation of the transistor is more sensitive to the doping of the source and gate work function compared to other physical parameters. Furthermore, the heterojunction TFETs show less sensitivity to physical parameter variations compared to the homojunction ones.

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Enabling Power-Efficient Designs with III-V Tunnel FETs

Cited by 13 publications

References 30 publications

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures

Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs

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