Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs

Abstract

In this paper, the impact of physical parameter variations on the electrical characteristics of III-V TFETs is investigated. The study is performed on the operations of two optimized ultra-thin 20nm double-gate transistors. The two device structures are InAs homojunction TFET and InAs-GaAs0.1Sb0.9 heterojunction TFET. The operation parameters are the ONcurrent, OFF-current, and threshold voltage. The investigation is performed at the device level, using a device simulator and the Monte-Carlo simulation approach is exploited to extract the distribution of electrical parameters in the presence of the process variation. The results reveal that the operation of the transistor is more sensitive to the doping of the source and gate work function compared to other physical parameters. Furthermore, the heterojunction TFETs show less sensitivity to physical parameter variations compared to the homojunction ones.

Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors

“…As discussed earlier, compared to MOSFETs, TFETs are more prone to the process variation. In [7], we investigated the impact of the process variation on the physical parameters of InAs TFET in the presence of the process variation. The investigation was performed by utilizing the Monte-Carlo simulations where the distributions of threshold voltage and ON-current were extracted for 1000 samples.…”

“…It is attributed to the fact that the ON-current and subsequently the threshold voltage of the TFET device have exponential dependences on the electric field making them more susceptible to the sources of variations. Table 2 summarizes the statistical parameters considered for the distributions of variation sources while Table 3 reports the means and standard deviations for the electrical parameters of the InAs TFET [7].…”

“…For instance, in [4], by comparing the changes of the ON-current for a Heterojunction TFET and Silicon MOSFET, it was concluded that TFETs were more sensitive to the process variation. In [7], the influence of the process variation on the electrical parameters of III-V TFET were studied and their statistical distributions were extracted and compared to those of MOSFET devices. To increase the reliability of TFET-based circuits, in [8], a heuristic algorithm for generating hybrid TFET-MOSFET based circuits was introduced.…”

Synthesis and characterization of n-type NiO:Al thin films for fabrication of p-n NiO homojunctions

“…Homogeneous transparent p-n junctions possess several advantages including: (1) a better interface quality between n-type and p-type layers, which can reduce the lattice mismatch between these two layers and improve the device's performance; (2) they remove the dependence on polarization charge, and avoid parasitic absorption within a light emitter structure [4][5][6]. In the last few years, in order to develop transparent p-n homojunctions, many efforts were paid on how to make n-type TCOs present p-type conductivity through doping suitable acceptors, and then combining these two layers together [7][8][9].…”